COHERENT SAMPLED READOUT CIRCUIT AND SIGNAL PROCESSOR FOR A CHARGE COUPLED DEVICE ARRAY

• US 3,781,574 A
• Filed: 10/20/1972
• Issued: 12/25/1973
• Est. Priority Date: 10/20/1972
• Status: Expired due to Term

• Current Assignee: David H. Mccann Jr, Franklyn C. Blaha, Ingham A.G. Mack, Marvin H. White
• Original Assignee: David H. Mccann Jr, Franklyn C. Blaha, Ingham A.G. Mack, Marvin H. White
• Inventors: McCann, David H. Jr., Blaha, Franklyn C., White, Marvin H., Mack, Ingham A. G.
• Primary Examiner(s): Craig, Jerry D.
• Application Number:
  US05/299,480
• Time in Patent Office: 431 Days
• Field of Search: 307/304,221D 328/165 317/235B,235G
• US Class Current: 327/284
• CPC Class Codes: G11C 19/285 Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
• CPC Class Codes: G11C 27/04 Shift registers
• CPC Class Codes: H01L 27/14831 Area CCD imagers
• CPC Class Codes: H01L 29/76816 Output structures

Abstract

A coherent sampled CMOS readout circuit and signal processor coupled to a CCD shift register operated by a two-phase minority carrier transfer clock system. The invention comprises a multiplex MIS switch, a reverse biased collection diode, an N channel MOSFET reset switch, a P channel MOSFET electrometer amplifier, and a sample and hold circuit, the configuration having four distinct operational timing sub-intervals within a clock period wherein the charge is shifted from one shift register bit to another and finally to the output bit. This removes the Nyquist noise associated with the reset switch, suppresses switching transients and 1/f surface noise to thereby improve the signal to noise ratio, i.e., dynamic range, for a CCD array and readout system.

Claims

1. A circuit for providing coherent readout and signal processing of charge coupled device (CCD) apparatus having a plurality of clocked transfer electrodes, comprising in combination:

a minority carrier detector circuit;

a minority carrier switch, including a control electrode coupled to a periodic control signal, located between said detector circuit and a transfer electrode of said CCD apparatus and being operable in response to said control signal during a third predetermined time subinterval of a minority carrier transfer clock period to gate a minority carrier charge packet into said detector circuit;

a field effect device of a first semiconductor type, operable as a reset switch, coupled between a Predetermined reference voltage and said detector circuit, and being operable in response to another periodic control signal for being rendered conductive during a first predetermined time subinterval of said clock period;

a field effect device of a second semiconductor type, operable as an amplifier, having an input electrode coupled to said first type field effect device and said detector circuit at a common circuit junction, said junction providing a node capacitance thereat which is charged to said reference voltage during said first time subinterval;

a sample and hold circuit including a first capacitor coupled to an output electrode of said second type field effect device, a first electrically operated switch device coupled to said first capacitor and being operable in response to still another periodic control signal for closing said switch means during a second predetermined time subinterval of said clock period whereby said first capacitor charges to said reference voltage appearing across said node capacitance, said minority carrier switch thereafter becoming operable during said third time subinterval wherein a minority carrier charge packet is coupled to said detector circuit and a signal voltage indicative thereof coupled to said first capacitor wherein a voltage subtraction process results, and a second electrically operated switch device operable in response to yet another periodic control signal for controlling said second switch during a fourth and last predetermined time subinterval of said clock period and a second capacitor coupled to said second switch device, said second capacitor sampling the voltage on said first capacitor during said fourth time subinterval and providing a video signal of said minority carrier signal thereacross.

2. The circuit as defined by claim 1 wherein said field effect devices of said first and second type comprise MOS transistors.

3. The circuit as defined by claim 2 wherein said MOS transistor of said first semiconductor type comprises an N channel device on said MOS transistor of said second semiconductor type comprises a P channel device.

4. The circuit as defined by claim 1 wherein said minority carrier detector circuit comprises a diode.

5. The circuit as defined by claim 4 wherein said diode comprises an integrated circuit diode including means for being reverse biased.

6. The circuit as defined by claim 4 wherein said field effect devices of said first and second semiconductor type comprise complementary MOS transistors each having a gate, a source, and a drain electrode and wherein said source electrode of the MOS transistor of said first semiconductor type is coupled to said reference voltage, said drain is connected to said diode, and said gate is connected to said another periodic control signal.

7. A circuit as defined by claim 6 wherein said MOS transistor of said first semiconductor type includes a substrate connected to a second predetermined reference voltage of greater magnitude than said first recited predetermined reference voltage and being of the same polarity as said first recited reference voltage.

8. The circuit as defined by claim 7, wherein said MOS transistor of said second semiconductor type includes a gate source and drain electrode and wherein said gate electrode comprises said input electrode, said source electrode comprises said output electrode coupled to said sample and hold circuit and said drain electrode is coupled to a bias potential.

9. The method of operating a charge coupled device circuit for providing coherent readout and signal processing of minority carrier signal packets, comprising the sequential steps of:

turning '"'"''"'"''"'"''"'"'on'"'"''"'"''"'"''"'"' a semiconductor reset switch and applying a reference voltage VR across a circuit node capacitance having a common connection with a minority carrier detection circuit, said voltage VR having an uncertainty expressed by the Nyquist noise voltage (Vn2)1/2 (KT/CN)1/2 when applied across said circuit node capacitance;

turning '"'"''"'"''"'"''"'"'off'"'"''"'"''"'"''"'"' said reset switch;

reading and holding said reference voltage appearing across said node capacitance by coupling a capacitor across said node capacitance;

uncoupling one side of said capacitor from one side of said node capacitance while remaining coupled to said detection circuit;

coupling a minority carrier signal packet into said detection circuit wherein said minority carriers change the charge state of said node capacitance and said capacitor; and

reading the voltage across said capacitor; and

sampling the voltage across said capacitor which comprises the difference between said reference voltage and the signal plus said reference voltage thereby removing said Nyquist voltage and switching transients from the signal output to improved dynamic range and provide 1/f noise filtering of the circuit.

10. The method of claim 9 wherein said step of coupling a capacitor across said node capacitance additionally includes clamping the voltage across said capacitor to a second reference voltage VC.