CORRELATORS USING SHIFT REGISTERS

• US 3,831,013 A
• Filed: 02/20/1973
• Issued: 08/20/1974
• Est. Priority Date: 02/20/1973
• Status: Expired due to Term

• Current Assignee: Harper John Whitehouse, James M. Alsup
• Original Assignee: Harper John Whitehouse, James M. Alsup
• Inventors: Alsup, James M., Whitehouse, Harper John
• Primary Examiner(s): Gruber, Felix D.
• Application Number:
  US05/333,608
• Time in Patent Office: 546 Days
• Field of Search: 235/181,150.53 340/347DA
• US Class Current: 708/425
• CPC Class Codes: G06J 1/005 for correlation; for convolution; for Z or Fourier Transform

Abstract

A correlator comprising a plurality of sets of multivibrators, each set being serially connected to form a shift register, each multivibrator having a set and a reset output lead, indicating its binary state. The plurality of shift registers comprise a J number of signal shift registers and, in the simplest embodiment, one reference shift register. Each multivibrator is connectable to a clocking source for shifting the states of the multivibrators. One of the multivibrators of each set, at one end of the series, the input multivibrator, is connectable to a source of signals, generally bilevel signals or pulses, each pulse having a predetermined time duration or a multiple thereof. The binary states of the multivibrators of the reference shift register, whether stationary or shifting with the incoming stream of bits, may be added to the binary states of corresponding multivibrators of the signal shift registers. Means are operatively connected to the output leads of corresponding multivibrators for summing the outputs of the multivibrators for each shift of binary states, the sum being a maximum for a particular combination, or coding, of binary states of the multivibrators of the shift registers. The means may comprise a plurality of modulo-2 adders, one for each of the multivibrators of the signal shift registers, and the same number of output resistors. The specific combination of connections are chosen in a manner so that, with applied input signals to the input multivibrators, a particular combination of binary states of the multivibrators will result in a maximum total output signal.

Claims

1. A correlator comprising:

a J number of signal shift registers, each shift register containing a K number of serially connected multivibrators in a row, all of the J number of rows of the JK multivibrators being arranged in K parallel columns;

a reference shift register, substantially identical to one of the signal shift registers;

each multivibrator of every signal and reference shift register being adapted for connection to a clocking source, for shifting the states of the multivibrators;

one of the multivibrators at one end of the series of each shift register being adapted for connection to a source of bilevel signals, or pulses, each pulse having a predetermined time duration or multiple thereof;

each multivibrator, of every signal and reference shift register having a set and reset output lead, at one of which appears one bilevel voltage, and at the other of which appears the other bilevel voltage, the voltages indicating the binary state of the multivibrator;

a K X J number of modulo-two adders whose inputs are the set or reset output leads of the signal and reference shift registers as determined from the logical expression Skj+Rk Skj Rk + Skj Rk, 1 <

OR = k <

OR = K, 1 <

OR = j <

OR = J, where the unbarred terms relate to the voltage level of the bilevel signal at a set, or reset, output lead;

the barred terms relate to the negative of the voltage level of the bilevel signal at a set, or reset, output lead;

Skj relates to the specific multivibrator of the signal register in the kth column and jth row; and

Rk relates to the kth multivibrator of the reference shift register;

an assembly of resistors comprising J groups, each group having K resistors, each of which has a resistance of KR ohms;

each resistor being connected by a first end to the output of each of the KJ modulo-2 adders;

each resistor of a group of resistors being connected by its second end to a common junction point;

a series connection of J-1 resistors, Each resistor having a value of R/2 ohms, connected across the junction points, one end of the series comprising an analog output; and

a resistor having a value of R ohms, one end being connected to the other end of the series connection of resistors, the other end being grounded.

2. The correlator according to claim 1, further comprising:

an analog-to-digital (A/D) converter, connectable to an input analog signal, having as output signals binary pulses corresponding to a least significant digit (LSD);

a number >

or = 0 of intermediate significant digits (ISD), and a most significant digit (MSD), the total number of significant digits equaling J, the output signals comprising the inputs to the signal shift registers; and

wherein the outputs of the shift registers of corresponding multivibrators from the reference and signal shift registers, one multivibrator from the reference shift register and one corresponding multivibrator at a time from the signal shift register being added together in modulo-2 fashion.

3. The correlator according to claim 1, further comprising:

an analog-to-digital (A/D) converter, connectable to an input analog signal having as output signals binary pulses correspoding to a least significant digit (LSD), a number >

or = 0 of intermediate significant digits (ISD), and a most significant digit (MSD), the total number of significant digits equaling J, the output signals comprising the inputs to the signal shift registers;

an additional number of reference shift registers, each substantially identical to the first-named reference shift register, the total number of reference shift registers equaling the number of signal shift registers;

each signal shift register being paired with a reference shift register by the KJ modulo-2 adders which are connected to their respective multivibrators;

all of the reference shift registers being connected to a common input terminal, so that the same input reference signal traverses all of the reference shift registers.

4. The correlator according to claim 1, further comprising:

a first analog-to-digital (A/D) converter, connectable to an input analog signal, having as output signals binary pulses corresponding to a least significant digit (LSD), a number >

or = 0 of intermediate significant digits (ISD) and a most significant digit (MSD), the total number of digits equaling J, the output signals comprising the inputs to the signal shift registers;

an additional number of reference shift registers, each substantially identical to the first-named reference shift register, the total number of reference shift registers not necessarily equal to the number of signal shift registers;

a plurality of assemblies of resistors, each assembly substantially identical to, and connected to modulo-2 adders in a manner similar as, the first-named assembly of resistors, the total number of assemblies equaling the number of reference shift registers N;

a second series connection of N-1 resistors, each resistor having a value of R/4 ohms, one end of the series, comprising the analog output, being connected to the ungrounded end of one of the assembly of resistors;

a grounded resistor having a value of R/2 ohms, the ungrounded end being connected to the other end of the second series connection of resistors and to another assembly of resistors;

the ungrounded end of each of the other J-2 assemblies of resistors being connected to one of the junction points between the resistors having a value of R/4 ohms;

a second analog-to-digital (A/D) converter, connectable to a second input analog signal, having as output signals binary pulses corresponding to a least significant digit (LSD), a number of intermediate significant digits (ISD) not necessarily the same as in the first A/D converter, and a most significant digit (MSD), the output signals comprising the inputs to the reference shift registers;

an additional plurality of modulo-2 addders, so that the total number is equal to the product of the number of signal shift registers by the number of reference shift registers times the number per register, corresponding multivibrators of the signal and reference shift registers comprising the inputs to their respective modulo-2 adders.

5. A correlator comprising:

an N number of analog delay lines, all having a common input and each having K taps, including an input and an ouptut tap;

an N number of reference shift registers, each containing a K number of serially connected multivibrators;

including an input multivibrator and an output multivibrator;

each multivibrator having a set and reset output lead, at one of which appears one bilevel voltage, and at the other of which appears one bilevel voltage, the voltages indicating the binary state of the multivibrator;

one of the multivibrators at one end of the series of each shift register, the input multivibrator, being connectable to a source of signals, generally a stream of bilevel signals, or pulses, each pulse having a predetermined time duration or multiple thereof;

one input multivibrator being connectable to a stream of pulses corresponding to a most significant digit (MSD), another to a least significant digit, and the other K-2 input multivibrators being connectable to streams of pulses corresponding to digits having values intermediate to these two;

each multivibrator of every reference shift register being connectable to a clocking source for shifting the states of the multivibrators in synchronism with the streams of pulses;

an NK number of analog multiplier circuits, one connected between corresponding taps of the delay line and multivibrators of the shift registers, e.g., between an input multivibrator and an input tap, the multiplier circuit comprising;

a voltage converter, whose input is the bilevel output voltage of a multivibrator, which converts either of two output voltages of equal magnitude but opposite polarity; and

a multiplier, whose inputs comprise the output voltage of the voltage converter and the output voltage of one of the taps, the output voltage of the multiplier being the product of the two input voltages;

a J number of signal summers, one associated with each of the delay lines and each of the shift registers, each signal summer having as inputs the outputs of its K associated analog multiplier circuits;

a resistor having a resistance of R ohms, one of whose ends is grounded, the other end being connected to that signal summer associated with the least significant digit;

an N-1 number of serially connected resistors, each having a resistance of R/2 ohms, one end of the series being connected to the ungrounded end of the grounded resistor, the other end of the series being connected to the output of that signal summer associated with the most significant digit, the other N-2 signal summers being connected to the N-2 junction points of the other N-1 resistors having a value of 1/2 R.