LINE VARIATION COMPENSATION SYSTEM FOR SYNCHRONIZED PCM DIGITAL SWITCHING

• US 3,839,599 A
• Filed: 11/10/1972
• Issued: 10/01/1974
• Est. Priority Date: 11/10/1972
• Status: Expired due to Term

• Current Assignee: AG Communication Systems Corp. (Nokia Corporation)
• Original Assignee: Satyan G. Pitroda
• Inventors: Pitroda, Satyan G.
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Psitos, Aristotelis M.
• Application Number:
  US05/305,412
• Time in Patent Office: 690 Days
• Field of Search: 178/69.5R,69.5DC 328/155 179/15BS 325/325
• US Class Current: 375/371
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
• CPC Class Codes: H04Q 2213/1336 Synchronisation

Abstract

A line synchronizer system including a digital phase detector subsystem, a frame detector subsystem and an elastic buffer register store subsystem is used within a digital PCM switching exchange to correct for timing or phase errors caused by cable temperature fluctuations and cumulative phase jitter. The line synchronizer system is utilized to correct for phase deviations of less than one bit position within the phase detector subsystem and provides for a predetermined number of bit position corrections within the elastic buffer register store subsystem. All timing corrections are bi-directional and are made during the framing bit which does not contain real information hence there is no loss of real information during a subsequent digital switching process. The line synchronizer system is described in connection with a frequency synchronized digital transmission loop using the master-slave synchronization method.

Claims

1. A digital phase detector for a line synchronizer system useful for providing phase adjustments of less than one pulse position to compensate for phase misalignments occurring within a synchronized digital PCM pulse data train arranged in a repeating time frame format and to be switched in a frame synchronized communication switching network having a master exchange clock frequency source, said digital phase detector including input time delay means receiving said PCM pulse train and imparting thereto a selectable magnitude of time delay, reference timing logic means receiving said master clock frequency and providing therefrom cyclically occurring first and second detector pulse trains having the trailing edges of the individual pulses of said first detector pulse train and the leading edges of the individual pulses of said second detector pulse train aligned with respect to time with the leading and trailing edges of the individual pulses of said PCM pulse train, respectively, phase detector logic means receiving said PCM pulse train from said input time delay means and said first and second detector pulse trains from said reference timing logic means and detecting simultaneous occurrences of said individual PCM pulses with the occurrences of the pulses of said first and second pulse trains for detecting phase shifts of said individual PCM pulses in positive and negative directions pulses respectively, said phase detector logic means providing first and second directional count pulses with the occurrences of detected positive and negative phase shifts, bidirectional counter means receiving said first and second directional count pulses and counting each thereof cumulatively, said counter means providing a plurality of first output signals representative of the accumulated numbers of first and second directional count pulses and providing a pair of second output signals representative of a predetermined number of accumulated first and second directional count pulses, respectively, and decoder logic means receiving selected ones of said first output signals and generating decorder output signals in response thereto, said decoder output signals being connected to said input time delay means for selecting the magnitude of time delay imparted to said PCM pulse train through decreasing and increasing said selectable magnitude of time delay with each of said positive and negative directional phase shifts, respectively, which generate said selected ones of said first output signals from said decoder logic means whereby phase misalignments of less than one pulse period are compensated for, said pair of second output signals being of opposite polarity corresponding to the predetermined numbers of accumulated first and second directional count pulses, respectively, and being provided to said line synchronizer system for use in the frame detecting of said PCM pulse train whereby phase misalignments of at least one pulse period are compensated for.

2. A digital phase detector as claimed in claim 1 wherein a preselected portion of each of said repeating frame periods for said PCM pulse train constitutes a framing bit period, said input time delay means includes a Plurality of access ouput data taps, each of said data taps providing therefrom said PCM pulse train with a different magnitude of time delay, only one of said access output data taps being connected at any given time to said phase detector logic means, said counter means counts cumulatively said positive and negative directional phase misalignments which occur within said framing bit period for said PCM pulse train, respectively, said detector logic means changes said access output data taps in a first direction corresponding to said counted positive directional phase misalignments, respectively, and in a second direction corresponding to said counted negative directional phase misalignments, respectively, for varying said selectable magnitude of time delay, and said pair of second output signals comprise a positive output signal which occurs for a preselected number of cumulative changes of said access output data taps in said first direction and a negative output signal which occurs for a corresponding preselected number of cumulative changes of said access output data taps in said second direction.

3. A digital phase detector as claimed in claim 2 wherein said time delay means is a three bit cell shift register having four access output data taps arranged with respect to said bit cells to provide 0*, 90*, 180* and 270* phase delays at said four access output data taps, respectively, out of 360* phase delay corresponding to 1 full pulse period.

4. A digital phase detector for detecting phase misalignments occurring within a synchronized digital PCM pulse data train arranged in repeating frame periods and to be switched in a communication switching network, said digital phase detector including input time delay means receiving said PCM pulse train and imparting thereto a selectable magnitude of time delay, reference timing logic means providing cyclically occurring first and second detector pulse trains having the trailing edges of the individual pulses of said first detector train and the leading edges of the individual pulses of said second detector train aligned with respect to time with the leading and trailing edges of the individual pulse of said PCM pulse train, respectively, detector logic means connected to receive said PCM pulse train from said input time delay means and to receive said first and second detector trains from said reference timing logic means and detecting positive and negative directional phase shifts through detecting simultaneous occurrences of said individual PCM pulses with the occurrences of the pulses of said first and said second detector trains, respectively, bidirectional counter means for counting cumulatively said positive and negative directional phase shifts which are detected within selected pulse periods for the repeating frame periods of said PCM pulse train, decoder logic means connected between said counter means and said time delay means for selectively decreasing and increasing said selectable magnitude of time delay upon each occurrence of a selected cumulative count of said positive and negative directional phase shifts, respectively, and gating means connected to said counter means for receiving a predetermined cumulative count of said positive and negative directional phase shifts and providing first and second output signals of opposite polarity corresponding to said predetermined counts which occur simultaneously with the occurrence of said first and second detector pulse trains, respectively.

5. A digital phase detector as claimed in claim 4 wherein said time delay means includes a plurality of access output data taps for providing therefrom said PCM pulse train having said selectable magnitude of time delay, respectively, with only one of said access output data taps being utilized at any given time, said logic means decreases said selectable magnitude of time delay through changing said access output data taps in a first direction corresponding to said coUnted positive directional phase misalignments, respectively, and increases said selectable magnitude of time delay through changing said access output data taps in a second direction corresponding to said counted negative directional phase misalignments, respectively, and said first output signal occurs for a preselected number of cumulative changes of said access output data taps in said first direction and said negative output signal thereof occurs for a corresponding preselected number of cumulative changes of said access output data taps in said second direction.