Gaming machine

• US 3,876,208 A
• Filed: 09/20/1973
• Issued: 04/08/1975
• Est. Priority Date: 09/20/1972
• Status: Expired due to Term

• Current Assignee: Gunter Wachtler, Peter Uri, Russi Tschernev, Wolfgang Straszer
• Original Assignee: Gunter Wachtler, Peter Uri, Russi Tschernev, Wolfgang Straszer
• Inventors: Wachtler, Gunter, Straszer, Wolfgang, Uri, Peter, Tschernev, Russi
• Primary Examiner(s): Shapiro, Paul E.
• Application Number:
  US05/399,333
• Time in Patent Office: 565 Days
• Field of Search: 273/1E,1R,1M,138A,139,142B,143R,143A,143B,143C,143D,143E
• US Class Current: 463/13
• CPC Class Codes: A63F 1/00 Card games aspects of games using an electronically generated display having two or more dimensions showing representations related to the game A63F13/00; card games played on a gaming machine G07F17/32
• CPC Class Codes: A63F 2001/008 adapted for being playable on a screen
• CPC Class Codes: G07F 17/32 for games, toys, sports, or amusements
• CPC Class Codes: G07F 17/3293 Card games, e.g. poker, canasta, black jack

Abstract

An electronically controlled gaming machine having poker-like rules of play, the machine comprises a matrix of card memory stages in rows and columns, each memory stage having three conditions and an output which is energised in one of the conditions. An indicator device includes a plurality of indicators one connected to each memory stage for illumination, when the output of the associated memory stage is energised. A dealing unit provides five sequential impulses to energise a random selection of five of the memory stages to represent five cards being dealt. A card return unit allows up to three of the memory stages so energised to be de-energised and subsequently blocked from re-energisation and the dealing unit can then be reoperated randomly to energise different memory stages until five stages are energised. Control circuits connected to the rows and columns of the memory stage matrix then determine the score in accordance with poker-like rules.

Claims

1. An electronically controlled gaming machine adapted to play card games with poker-like rules of play, comprising:

an indicating unit having a plurality of selectively operable cardrepresenting indicator devices, one for each card of a group of possible cards;

a card memory having a plurality of memory stages one for each indicator device, each card memory stage having an input thereto and an output connected to the associated indicator device, and being operable to assume one of three memory conditions, a reception condition, a memory condition, and a blocking condition, each said memory stage operating to produce an output signal when in said memory condition and no output signal when in said reception condition or said blocking condition, and switching to said memory condition on the occurrence of a signal on said input if it is in said reception condition but not if it is in said blocking condition, a dealing unit having a plurality of outputs each connected to the inputs of a respective card memory stage, said dealing unit comprising in combination;

a random signal generator, means connecting said random signal generator to all said outputs from said dealing unit, means for cyclically enabling said outputs from said dealing unit whereby an output signal on one of said output lines is produced if a random signal occurs when said one of said output lines is enabled, said output signal operating to switch the card memory stage connected to said one of said output lines to its memory condition if it is in its reception condition, a counter circuit connected to the outputs of all said memory stages and operable to produce an output pulse when a predetermined number of memory stages have been switched to their memory conditions, and means interconnecting said counter and said random signal generator to inhibit the generation of further random signals upon the occurrence of said output signal from said counter indicating that said predetermined number of memory stages have been switched to their memory condition to represent the dealing of a predetermined number of cards, a card return unit having, a plurality of operating members each connected to a respective memory stage and operating, when actuated, to switch the associated memory stage to its blocking condition from its memory condition, and a new deal operating member connected to said dealing unit and operable to energise said dealing unit, when actuated, to randomly switch further memory stages to their said memory conditions until the said predetermined number of memory stages in the memory condition is re-established, a stake unit having a coin or token receiving mechanism and means for producing an output signal when coins or tokens are held in said stake unit, inhibit means interconnecting the output of said stake unit and said dealing unit, operating to inhibit said dealing unit unless there is an output signal from said stake unit, and result read-out means connected to said memory stages and operating to indicate the score obtained in dependence on which of said memory stages are in said memory condition.

2. The gaming machine of claim 1, wherein said dealing unit includes a plurality of multiple input AND gates the outputs from which constitute the outputs of said dealing unit and are connected to the inputs of corresponding card memory stages, and wherein each said card memory stage comprises first and second bistable circuits each having set and reset inputs and set and reset outputs, the set input of said first bistable circuit being connected to said dealing unit and the set input of said second bistable circuit being connected to a corresponding operating member of said card return unit, said set output of said first bistable circuit being connected to the corresponding indicating device, said reset outputs of both said first and said second bistable circuits being connected to respective inputs of the corresponding multiple input AND gate, whereby said memory stage is in said reception condition when both said bistable circuits are in their reset state, in said memory condition when said first bistable circuit is in its set state and said second bistable circuit is in its reset state, and in its blocking condition when said first bistable circuit is in its reset state and said second bistable circuit is in its set state.

3. The gaming machine of claim 2, wherein said means for cyclically enabling said outputs of said dealing unit comprise:

an oscillator producing a train of output pulses, a counter having a serial input connected to the output from said oscillator, said counter having a plurality of parallel binary outputs on which appear, in binary form, signals representing the number of pulses counted by said counter, means interconnecting said parallel outputs of said counter and some of the inputs of each of said multiple input AND gates the remaining input of said multiple input AND gates being connected to said random signal generator whereby, when said first and second bistable circuits of the corresponding card memory stages are both in a reset state said multiple input AND gates are enabled by said counter when it has counted a corresponding number of pulses from said oscillator circuit.

4. The gaming machine of claim 2, wherein said dealing means additionally comprises a reversible counter having a forward input and a reverse input, and an output connected to a first decoder circuit having two outputs, one energised on a forward count of five signals and the other energised on a forward count of two signals, means interconnecting the set output of the first bistable circuit of each said memory stage of said card memory to said forward input of said reversible counter, and means interconnecting said one output of said first decoder circuit with said inhibit means whereby said dealing unit is stopped after five memory stages have been switched to their memory condition, representing five cards dealt.

5. The gaming machine of claim 1 wherein said inhibit means includes a third bistable circuit having set and reset inputs and set and reset outputs, means connecting said set input to said one output of said first decoding circuit, means connecting said reset input to said other output from said decoding circuit, and an AND gate having one input connected to said oscillator and an output connected to said counter, another input of said AND gate being connected to said reset output of said third bistable circuit whereby said AND gate is enabled when said third bistable circuit is in its reset state, and disabled when said third bistable circuit is switched to its set state upon the occurrence of an output signal on the said one output of said decoder circuit.

6. The gaming machine of claim 1 wherein said operating members of said card return unit each comprise a single pole reversing switch for each memory stage, resilient biasing means biasing each reversing switch to one position, all said reversing switches being connected in series in a line when in said one position, and means applying a card return signal to the movable contact of the reversing switch at one end of said line of switches for a predetermined time after the dealing unit has stopped.

7. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result read-out unit has a flush determining circuit comprising in combination a column member determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column, an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition, means for providing a train of clock pulses to the serial input of said shift register, a counter connected to said serial output of said shift register, and a second decoder circuit connected to the output of said counter circuit, said second decoder having first, second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2,3 or 5 stages of said shift register in a binary 1 condition, a sequence determining circuit comprising six first invertor circuits, three of which are connected to the outputs of the three first OR gates connected to the three columns at a first end of said memory stage matrix and three of which are connected to the three first OR gates connected to the three columns at a second end of said memory stage matrix, four first NAND gates each having three inputs, the outputs of said first invertor circuits being connected in different groups of three to said inputs of said first NAND gates whereby each NAND gate produces an output signal if the corresponding columns of said memory stage matrix having no memory stage in said memory condition leave five remaining columns in which it is possible for memory stages to be in said memory condition to form a sequence of five, and no signal if the distribution of columns having no memory stage in said memory condition is such that no sequence of five different adjacent columns can have memory stages in said memory condition, and a first AND gate having five inputs, four of said inputs being connected to the outputs of said first NAND gates and the fifth being connected to said third output of said second decoder circuit whereby said first AND gate produces an output signal when said memory stages of said matrix in said memory condition all lie in five different adjacent columns, a line number determining circuit operating to produce an output signal when all the memory stages of said matrix in said memory condition are disposed in a single line, said circuit comprising eight second OR gates each having eight inputs connected to the outputs of respective memory stages in a corresponding line, a threshold circuit having eight inputs connected to the outputs of the eight second OR circuits and operating to produce an output signal if there is a signal on two or more inputs thereof, and a second invertor circuit connected to the output of said threshold circuit, the output of said second invertor circuit producing an output signal only when a signal is present on one input only of said threshold circuit, a third invertor circuit connected to the output of said first AND gate, a fourth invertor circuit connected to the output of said second invertor circuit, and a second AND gate having three inputs respectively connected to the outputs of said second and third invertor circuits and said third output of said second decoder circuit.

8. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result read-out unit has a straight flush determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the ouputs of the memory stages of a corresponding cloumn, an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a mamory condition, means for providing a train of clock pulses to the serial input of said shift register, a counter connected to said serial output of said shift register, and a second decoder circuit connected to the output of said counter circuit, said second decoder having first, second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition, a sequence determining circuit comprising six first invertor circuits, three of which are connected to the ouputs of the three first OR gates connected to the three columns at a first end of said memory stage matrix and three of which are connected to the three first OR gates connected to the three columns at a second end of said memory stage matrix, four first NAND gates each having three inputs, the outputs of said first invertor circuits being connected in different groups of three to said inputs of said first NAND gates whereby each NAND gate produces an output signal if the corresponding columns of said memory stage matrix having no memory stage in said memory condition leave five remaining columns in which it is possible for memory stages to be in said memory condition to form a sequence of five, and no signal if the distribution of columns having no memory stage in said memory condition is such that no sequence of five different adjacent columns can have memory stages in said memory condition, and a first AND gate having five inputs, four of said inputs being connected to the outputs of said first NAND gates and the fifth being connected to said third ouput of said second decoder circuit whereby said first AND gate produces an output signal when said memory stages of said matrix in said memory condition all lie in five different adjacent columns, a fifth invertor circuit connected to the output of that one of said first OR gates the inputs of which are connected to the column of said matrix of memory stages representing aces, and a third AND gate having three inputs respectively connected to said third output of said second decoder circuit, said output of said first ANd gate and the output of said fifth invertor circuit.

9. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result read-out unit has a royal flush determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column, an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition, means for providing a train of clock pulses to the serial input of said shift register, a counter connected to said serial output of said shift register, and a second decoder circuit connected to the output of said counter circuit, said second decoder having first, second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition, a sequence determining circuit comprising six first invertor circuits, three of which are connected to the outputs of the three first OR gates connected to the three columns at a first end of said memory stage matrix and three of which are connected to the three first OR gates connected to the three columns at a second end of said memory stage matrix, four first NAND gates each having three inputs, the outputs of said first invertor circuits being connected in different groups of three to said inputs of said first NAND gates whereby each NAND gate produces an output signal if the corresponding columns of said memory stage matrix having no memory stage in said memory condition leave five remaining columns in which it is possible for memory stages to be in said memory condition to form a sequence of five, and no signal if the distribution of columns having no memory stage in said memory condition is such that no sequence of five different adjacent columns can have memory stages in said memory condition, and a first AND gate having five inputs, four of said inputs being connected to the outputs of said first NAND gates and the fifth being connected to said third output of said second decoder circuit whereby said first AND gate produces an output signal when said memory stages of said matrix in said memory condition all lie in five different adjacent columns, and a fourth AND gate having three inputs respectively connected to said third output of said second decoder circuit, said output of said first AND gate and the output of that one of said first OR gates the inputs of which are connected to the column of said matrix of memory stages representing aces.

10. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result read-out unit has a poker determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column, an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stges in the associated column is in a memory condition, means for providing a train of clock pulses to the serial input of said shift register, a counter connected to said serial output of said shift register, and a second decoder circuit connected to the output of said counter circuit, said second decoder having first, second and third outputs respectively, energised an a output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition, eight fifth AND gates each having four inputs connected to the outputs of respective memory stages in corresponding columns of said matrix whereby a fifth AND gate produces an output signal if all said memory stages in the corresponding column are in said memory condition, and a third OR gate having eight inputs connected to the outputs of said eight fifth AND gates, said third OR gate producing an output signal when all the memory stages of any column of said matrix are all in said memory condition, a sixth AND gate having two inputs connected to the outputs of two of the memory stages in the column of said memory matrix representing aces, a sixth invertor connected to the output of said sixth AND gate, and a seventh AND gate having two inputs respectively connected to the outputs of said sixth invertor circuit and said second OR gate, said seventh AND gate producing an output signal representing poker.

11. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result read-out unit has an ace poker determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column, an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition, means for providing a train of clock pulses to the serial input of said shift register, a counter connected to said serial output of said shift register, and a second decoder circuit connected to the output of said counter circuit, said second decoder having first, second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition, eight fifth AND gates each having four inputs connected to the outputs of respective memory stages in corresponding columns of said matrix whereby a fifth AND gate produces an output signal if all said memory stages in the corresponding column are in said memory condition, and a third OR gate having eight inputs connected to the outputs of said eight fifth AND gates, said third OR gate producing an output signal when all the memory stages of any column of said matrix are all in said memory condition, a sixth AND gate having two inputs connected to the outputs of two of the memory stages in the column representing aces, and an eighth AND gate having two inputs connected respectively to the output of said sixth AND gate and to the output of said second OR gate and producing an output signal representing ace poker.

12. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result read-out unit has a full house determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column, an eight stage shift register having a serial input a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition, means for providing a train of clock pulses to the serial input of said shift register, a counter connected to said serial output of said shift register, and a second decoder circuit connected to the output of said counter circuit, said second decoder having first second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition, eight fifth AND gates each having four inputs connected to the outputs of respective memory stages in corresponding columns of said matrix whereby a fifth AND gate produces an output signal if all said memory stages in the corresponding column are in said memory condition, and a third OR gate having eight inputs connected to the outputs of said eight fifth AND gates, said third OR gate producing an output signal when all the memory stages of any column of said matrix are all in said memory condition, a seventh invertor circuit connected to the output of said third OR gate, eight groups of three ninth AND gates each having three inputs, the inputs of each group being connected to the memory stages of a corresponding column whereby an output signal from one of said ninth AND gates of a group is produced if any three of said memory stages in said corresponding column are in said memory condition, a group of eight fourth OR gates connected to the outputs or respective groups of said ninth AND gates, a fifth OR gate connected to the outputs of said fourth OR gates, and a tenth AND gate having three inputs respectively connected to the outputs of said seventh inverter circuit, the output of said fourth OR gate and the first output of said decoder circuit, said tenth AND gate producing an output signal representing full house.

13. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result read-out unit has a three-of-a-kind determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column, an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition, means for providing a train of clock pulses to the serial input of said shift register, a counter connected to said serial output of said shift register, and a second decoder circuit connected to the output of said counter circuit, said second decoder having first second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition, eight groups of three ninth AND gates each having three inputs, the inputs of each group being connected to the memory stages of a corresponding column whereby an output signal from one of said ninth AND gates of a group is produced if any three of said memory stages in said corresponding column are in said memory condition, a group of eight fourth OR gates connected to the outputs of respective groups of said ninth AND gates, a fifth OR gate connected to the outputs of said fourth OR gates, and an eleventh AND gate having two inputs respectively connected to said second output of said second decoder circuit and the output of said fifth OR gate.

14. The gaming machine of claim 1 wherein said stake unit comprises, a coin or token checking device having an output which is energised upon insertion of a valid coin or token into said coin or token checking device, a coin or token payout device, a credit meter having a reversible counter and an indicator showing the count in the counter, said counter having a forward input connected to the output of said coin or token checking device and a backward input connected to said coin or token payout device and to said card return unit, a decoder circuit having an output which is energised when the count in said counter is zero, and a payout inhibit device connected to said output of said decoder and operating to inhibit payout when the count in said counter is zero.