Master clock with electronic memory

• US 3,889,461 A
• Filed: 10/19/1973
• Issued: 06/17/1975
• Est. Priority Date: 10/19/1973
• Status: Expired due to Term

• Current Assignee: Olivier Chanson, Raymond Marti
• Original Assignee: Olivier Chanson, Raymond Marti
• Inventors: Marti, Raymond, Chanson, Olivier
• Primary Examiner(s): Tomsky, Stephen J.
• Assistant Examiner(s): Weldon, U.
• Application Number:
  US05/407,963
• Time in Patent Office: 606 Days
• Field of Search: 58/152H,24R,24A,25,26R,26B,33,23R,34,35R
• US Class Current: 368/52
• CPC Class Codes: G04C 13/02 Circuit arrangements; Electric clock installations
• CPC Class Codes: G04G 19/10 Arrangements for supplying back-up power
• CPC Class Codes: G04G 9/0005 Transmission of control signals

Abstract

A master clock having an oscillator, a divider, a signal shaper, an output amplifier, and power feed either by means of an electric circuit or by means of a battery at the time of power failure in the circuit. A detector for circuit voltage is provided which upon a fall in circuit voltage switches signals from the output of the divider to an electronic memory. Upon reestablishment of power in the circuit, the time signals are fed out of the memory at an accelerated rate to cause the secondary clocks controlled by the master clock to catch up. It is thus possible to use only a small and inexpensive standby battery for use during power failure.

Claims

1. In a master clock comprising an oscillator, a divider connected to the output of said oscillator, a signal shaper, an output amplifier receiving signals from said signal shaper, and means to supply power to the clock from a power circuit through a battery to said oscillator and divider and shaper and directly to the rest of the clock;

the improvement comprising a voltage detector for said circuit, a memory and a logic device receiving signals from the voltage detector and transmitting signals to said signal shaper, said logic device having means switching the output of the divider from the signal shaper to the memory when the circuit voltage falls below a predetermined value, said logic device also having means responsive to re-establishment of voltage in said circuit above said predetermined value to feed out signals stored in said memory to said signal shaper at a faster rate than their rate of storage.

2. A master clock as claimed in claim 1, said logic device also having means preventing feed out of signals from said memory at the time of passage of normal minute signals of the clock.