Time division multiplex system for a motor vehicle

• US 3,891,965 A
• Filed: 09/16/1974
• Issued: 06/24/1975
• Est. Priority Date: 09/16/1974
• Status: Expired due to Term

• Current Assignee: Thaddeus Schroeder
• Original Assignee: Thaddeus Schroeder
• Inventors: Schroeder, Thaddeus
• Primary Examiner(s): Waring, Alvin H.
• Application Number:
  US05/506,224
• Time in Patent Office: 281 Days
• Field of Search: 340/52F,179,180,181,182,183,184,21R,413 307/1R
• US Class Current: 340/459
• CPC Class Codes: B60R 16/0315 using multiplexing techniques multiplexing for transmission of signals G08C15/00; multiplexing for electrical communication in general H04J
• CPC Class Codes: G08C 15/12 the signals being represented by pulse characteristics in transmission link

Abstract

A time division multiplex system for a motor vehicle which includes a single cable arranged around the vehicle and comprising a power conductor, an information conductor, and a plurality of address lines. Various sender-receiver sets are addressed in appropriate time slots by an address generator so that information is transferred from respective information sources to corresponding load devices. Complementary codes are assigned to each sender-receiver set so that in the event of shorting or open circuiting of an address line the system will remain operational. Monitoring circuitry is provided for informing the operator of such an event. In a second embodiment a pair of power conductors and a pair of information conductors are provided for improving the reliability of the system.

Claims

1. In a motor vehicle having a source of direct current, a plurality of information input means and associated load means, a time division multiplex system for controlling the application of current to said load means comprising:

a sender-receiver set for each input means and associated load means;

address generator means for successively generating a plurality of multibit binary words;

conductor cable means including a power conductor for supplying current from said source to said address generator means and each of said sender-receiver sets, said cable means including an information conductor interconnecting each sender-receiver set, said cable means further including a plurality of address conductors interconnecting said address generator means with said sender-receiver sets, the number of address conductors corresponding to the number of bits in each of said plurality of multibit binary words;

each of said sender-receiver sets including address decoder means responsive to different binary words whereby information may be communicated between respective sender-receiver sets during the time the respective sender-receiver sets are being addressed;

the receiver in each sender-receiver set controlling the application of current to the associated load means in response to the information received from the associated sender.

2. The invention defined in claim 1 wherein said system further includes circuitry for monitoring and indicating a fault condition with respect to any of said plurality of address conductors and including first, second, and third analog gate means connecting said first analog gate between an originating point and a terminating point of an address line, a pullDown resistor connected between said terminating point and a reference potential, first address decoder means for controlling said first, second, and third analog gates;

said first decoder means opening said first analog gate and closing said second and third analog gates in response to a predetermined one of said multibit binary words, first and second flip-flops connected with said second and third analog gate means respectively and adapted to be clocked from said first address decoder means for storing the logic level at said originating and terminating point, a fourth analog gate, second address decoder means responsive to a multibit binary word different from the word to which said first address decoder means responds for controlling said fourth analog gate, indicator means responsive to the output of said fourth analog gate, logic means responsive to the state of said first or second flip-flops and providing an input to said fourth analog gate whereby said indicator means is energized if said address line is shorted to ground or open circuited.

3. In a motor vehicle having a source of direct current, a plurality of information input means and associated load means, a time division multiplex system for controlling the application of current to said load means comprising:

a sender-receiver set for each input means and associated load means;

address generator means comprising an iterative Gray Code counter and clock means for driving said counter to successively generate a plurality of multibit binary words;

conductor cable means including a power conductor for supplying current from said source to said address generator means and each of said sender-receiver sets, said cable means including an information conductor interconnecting each sender-receiver sets, said cable means further including a plurality of address conductors interconnecting said address generator means with said sender-receiver sets, the number of address conductors corresponding to the number of bits in each of said plurality of multibit binary words;

each of said sender-receiver sets including address decoder means responsive to complementary ones of said binary words whereby information may be communicated between respective sender-receiver sets during the time the respective sender-receiver sets are being addressed;

the receiver in each sender-receiver set controlling the application of current to the associated load means in response to the information received from the associated sender.

4. In a motor vehicle having a source of direct current, a plurality of information input means and associated load means, a time division multiplex system for controlling the application of current to said load means comprising:

a sender-receiver set for each input means and associated load means;

address generator means for successively generating a plurality of multibit binary words, said generator means including an iterative Gray code counter and clock means for driving said counter to successively generate a plurality of multibit binary words;

conductor cable means including a pair of power conductors, separate fuse means connecting respective ones of said power conductors to said source, a plurality of pairs of back-to-back diodes interconnecting said power conductors, means interconnecting said address generator means and each of said sender-receiver sets to a junction between certain ones of said back-to-back diodes, said cable means further including an information conductor interconnecting said sender-receiver sets, said cable means further including a plurality of address conductors interconnecting said address generator means with each of saiad sender-receiver sets, the number of address conductors corresponding to the number of bits in each of said plurality of multibit binary words;

each of said sender-receiver sets including address decoder means responsive to complementary ones of said binary words whereby information may be communicated betweeN respective sender-receiver sets twice during any address cycle;

the receiver in each of said sender-receiver sets controlling the application of current to the associated load means in accordance with the information received from the associated sender.