High-efficiency tuned switching power amplifier

• US 3,919,656 A
• Filed: 04/23/1973
• Issued: 11/11/1975
• Est. Priority Date: 04/23/1973
• Status: Expired due to Term

• Current Assignee: Alan D. Sokal, Nathan O. Sokal
• Original Assignee: Alan D. Sokal, Nathan O. Sokal
• Inventors: Sokal, Nathan O., Sokal, Alan D.
• Primary Examiner(s): Kaufman, Nathan
• Application Number:
  US05/353,588
• Time in Patent Office: 932 Days
• Field of Search: 330/192,27A,31 307/297,243
• US Class Current: 330/51
• CPC Class Codes: H03F 3/2176 Class E amplifiers

Abstract

A high efficiency tuned switching power amplifier employs an active device switch driven at a frequency determined by an a.c. input signal. The active device switch controls the application of direct current power to a load through a resonant load network. The load network is substantially nonresistive and its resonance minimizes power loss by insuring that in the transition of the switch from '"'"''"'"''"'"''"'"'on'"'"''"'"''"'"''"'"' to '"'"''"'"''"'"''"'"'off,'"'"''"'"''"'"''"'"' the voltage across the switch remains low (viz. substantially zero) until the current through the switch has fallen to zero (viz. current flow ceases). The network, in addition, insures that the voltage across the switch is zero at the end of the off state so that current flow through the switch recommences when there is substantially zero voltage across the switch and that that voltage remains substantially zero while current flow through the switch continues. The network further causes the voltage waveform across the switch to have zero or nearly zero time derivative at the end of the off state.

Claims

1. In apparatus of the tuned switching type for the highefficiency generation of alternating-current power, having A. an active device switch having a low-impedance on state and a high-impedance off state, B. driver means for causing the switch to commute periodically between the two states, C. a load network having an input port and an output port, said input port being connected in series with the switch, D. a load coupled to the output port of the load network, and E. means for supplying D.C. power to the series combination of the switch and the load network input port, the aforementioned elements being connected such that an inductive element is disposed in the D.C. path which extends to the switch from the means for supplying the D.C. power, and wherein the subcombination of the load network and the load includes F. A damped resonant circuit, operative at least while the switch is in the off state, in which the damping is effected at least in part by the resistance of the load, said damped resonant circuit including 1. at least one capacitive element whose capacitive reactance at the operating frequency is apprecIable, and 2. at least one inductive element whose inductive susceptance at the operating frequency is appreciable, the improvement wherein the values of the elements in the subcombination of the load and the load network are such that the voltage across the switch is substantially zero at the end of the off state, the voltage across the switch is substantially zero during the time the switch is in transition from the off state to the on state, and the time derivative of the voltage across the switch is substantially zero at the end of the off state.

2. The improvement according to claim 1, further characterized in that the combination of the load network and the load includes a circuit which is substantially an impedance-transform of the following circuit:

disposed in parallel in the A.C. path across the switch are a first branch and a second branch, A. the first branch comprising the series combination of i. a resistive element of resistance R at the operating frequency, ii. an inductive element of inductance

3. The improvement according to claim 1, further characterized in that the switch '"'"''"'"''"'"''"'"'on'"'"''"'"''"'"''"'"' duty ratio is substantially 50%, and that the subcombination of the load network and the load includes a circuit which is substantially an impedance-transform of the following circuit:

disposed in parallel in the A.C. path across the switch are a first branch and a second branch, A. the first branch comprising the series combination of i. a resistive element of resistance R at the operating frequency, ii. an inductive element of inductance

4. The improvement according to claim 1, wherein the A.C. input admittance of the subcombination of the load network and the load, measured at the input port of the load network, is substantially

5. The improvement according to claim 4 wherein the switch on duty ratio is substantially 50% and a. x is defined as 1+1/QL, and b. y is defined as (1+1/QL)/6.3.

6. The improvement according to claim 1 wherein the load network further includes means for storing electric charge, said means being disposed in the A.C. path across the active device switch, and the element values in the subcombination of the network load and the load are further such that when the switch is in transition from the on state to the off state, any substantial increase in voltage across the switch is delayed at least until the current through the switch has fallen to substantially zero.

7. The improvement according to claim 6, further characterized in that the combination of the load network and the load includes a circuit which is substantially an impedance-transform of the following circuit:

disposed in parallel in the A.C. path across the switch are a first branch and a second branch, A. the first branch comprising the series combination of i. a resistive element of resistance R at the operating frequency, ii. an inductive element of inductance

8. The improvement according to claim 6, further characterized in that the switch on duty ratio is substantially 50%, and that the subcombination of the load network and the load includes a circuit which is substantially an impedance-transform of the following circuit:

disposed in parallel in the A.C. path across the switch are a first branch and a second branch, A. the first branch comprising the series combination of i. a resistive element of resistance R at the operating frequency, ii. an inductive element of inductance

9. The improvement according to claim 6, wherein the A.C. input admittance of the subcombination of the load network and the load, measured at the input port of the load network, is substantially

10. The improvement according to claim 9 wherein the switch on duty ratio is substantially 50% and a. x is defined as 1+1/QL, and b. y is defined as (1+1/QL)/6.3.