Variable tap weight convolution filter

• US 3,935,439 A
• Filed: 07/12/1974
• Issued: 01/27/1976
• Est. Priority Date: 07/12/1974
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Buss, Dennis Darcy, Bailey, Walter Howard
• Primary Examiner(s): Gruber, Felix D.
• Application Number:
  US05/487,105
• Time in Patent Office: 564 Days
• Field of Search: 235/181, 235/150.53, 235/177, 235/193, 235/197, 357/24, 307/304, 307/221
• US Class Current: 708/818
• CPC Class Codes: G06G 7/1907 using charge transfer devices
• CPC Class Codes: H03H 15/02 using analogue shift registers
• CPC Class Codes: H03H 2015/026 Matched filters in charge domain

Abstract

A variable tap weight convolution filter comprised of charge transfer devices which may be charge coupled devices, bucket brigade devices or a combination of the two, for performing convolutions of an input signal with tap weights from a second input signal, said tap weights varying as a function of time.

Claims

1. Analog signal processing apparatus comprising:

a first analog charge transfer device for receiving sampled values of a first analog signal and storing said sampled values at charge storage sites of said charge transfer device;

a second analog charge transfer device for receiving sampled values of a second analog signal and storing said sampled values at charge storage sites of said charge transfer device;

each of said first and second analog charge transfer devices including a like plurality of stages each including a plurality of charge storage sites, at each said stage a plurality of electrodes for receiving multi-phase clock pulses to transfer said analog signal samples along said charge transfer device;

analog signal multiplier means for corresponding pairs of said first and second analog charge transfer devices, for producing an output signal proportional to the product of first and second analog signal samples stored at the said corresponding stages of said first and second charge transfer devices, said analog signal multiplier means including first and second input electrodes electrically coupled to said corresponding stage of said first and second charge transfer devices for nondestructive detection of amplitudes of analog signal samples stored at said respective corresponding stages to apply analog pulse inputs to said first and second input electrodes; and

means for summing the outputs of said multiplier means.

2. The device of claim 1, wherein said charge transfer devices are charge coupled devices.

3. The device of claim 1, wherein said charge transfer devices are bucket brigade devices.

4. The device of claim 1, wherein said charge transfer devices comprise a combination of charge coupled devices and bucket brigade devices.

5. Analog signal processing apparatus, according to claim 1, wherein said signal multiplier means for each of said corresponding pairs of stages includes first and second insulated gate field effect transistor amplifier structures having channels connected in series between a supply voltage line and a common output signal line, means electrically coupling the gate of said first transistor to a predetermined charge storage site of said stage of said first charge transfer device for non-destructive detection of the amplitude of a signal sample stored at said particular storage site to apply an analog input pulse to said first transistor;

and means electrically coupling the gate of said second transistor to a particular charge storage site of the corresponding stage of said second charge transfer device for non-destructive detection of a signal sample stored at said corresponding particular storage site to apply an analog input pulse to said second transistor; and

means for connecting said common output signal line to said means for summing the output of said multipliers.

6. The device of claim 5, wherein said charge transfer devices are charge coupled devices and said field effect transistor amplifiers are floating gate amplifiers, portions of the floating gates of said first transistor amplifier and of said second transistor amplifier being located adjacent respective individual first and second charge coupled device shift register electrodes for receiving a predetermined phase of said multi-phase clock pulses, and including means for applying a predetermined reference pulse level to said floating gates during said predetermined phase of said multi-phase clock pulses.

7. The device of claim 5, wherein said charge transfer devices are charge coupled devices and said field effect transistor amplifiers are floating diffusion amplifiers.

8. The device of claim 5, wherein said charge transfer devices are bucket brigade devices and said field effect transistor amplifiers are floating diffusion amplifiers.

9. The device of claim 5, wherein one of said charge transfer devices is a charge coupled device and the other of said charge transfer devices is a bucket brigade device, and wherein the particular charge storage site of each stage of said charge coupled device includes a floating gate coupled to the gate of one of said first and second transistors of the signal multiplier means coupled to that stage and including means for applying a predetermined reference pulse to said floating gates when an analog signal sample is stored at the said particular storage sites of said charge coupled device shift register.

10. The device of claim 5, wherein one of said charge transfer devices is a charge coupled device and the other of said charge transfer devices is a bucket brigade device, and wherein the particular charge storage site of each stage of said charge coupled device includes a floating diffusion electrically coupled to the gate of one of said first and second transistors of said signal multiplier means coupled to that stage.

11. The device of claim 5, wherein one of said charge transfer devices is a charge coupled device and the other of said charge transfer devices is a bucket brigade device and wherein the particular charge storage site of each stage of said bucket brigade device includes a floating diffusion coupled to the gate of one of said first and second transistors of said signal multiplier means coupled to that stage.

12. Analog signal processing apparatus comprising:

a first charge transfer device analog shift register for receiving a first analog signal (V_G) added to a non-zero d.c. reference level (B) to provide a unipolar signal input to said analog shift register and for storing a plurality of sampled values of said unipolar signal input at charge storage sites of said first shift register;

inverter means for inverting said unipolar signal input, said inverter means connected in parallel with said first charge transfer device;

a second charge transfer device analog shift register for receiving a second analog signal and for storing a plurality of sampled values of said second analog signal at charge storage sites of said second charge transfer device;

a third charge transfer device analog shift register for receiving said inverted unipolar signal input from said inverter means;

each of said charge transfer device shift registers including a like plurality of stages each having a plurality of charge storage sites, at each said stage a plurality of electrodes for receiving multi-phase clock pulses to transfer said signal samples along said charge transfer device;

first analog signal multiplier means for corresponding pairs of stages of said first and second charge transfer devices, for producing an output signal proportional to the product of first and second signal samples stored at the said corresponding stages of said first and second charge transfer devices, said first signal multiplier means including first and second input electrodes electrically coupled to said corresponding stages of said first and second charge transfer devices for non-destructive detection of amplitudes of signal samples stored at said corresponding stages to apply analog pulse inputs to said first and second input electrodes;

second analog signal multiplier means for corresponding pairs of stages of said second and third charge transfer devices, for producing an output signal proportional to the product of second and third signal samples stored at the said corresponding stages of said second and third charge transfer devices, said second signal multiplier means including first and second inputs electrically coupled to said corresponding stages of said second and third charge transfer devices for non-destructive detection of amplitudes of signal samples stored at said corresponding stages to apply analog pulse inputs to said first and second input electrodes; and

signal summation means for algebraically summing the outputs of said first and second signal multiplier means to eliminate said d.c. reference level (B) added to said first analog signal and for producing an output signal.

13. The device of claim 12, wherein said charge transfer devices are charge coupled devices.

14. The device of claim 12, wherein said charge transfer devices are bucket brigade devices.

15. The device of claim 12, wherein at least one of said charge transfer devices comprise a charge coupled device and the or each other said charge transfer device comprises a bucket brigade device.

16. Analog signal processing apparatus comprising:

a first charge transfer device analog shift register for receiving a first analog signal (V_G) having a predetermined non-zero d.c. reference level (B) to provide a unipolar signal input and storing a plurality of sampled values of said unipolar signal input (V_G + B) at charge storage sites of said first shift register;

a second charge transfer device analog shift register for receiving a second analog signal (V_S) and storing a plurality of sampled values of said second analog signal at charge storage sites of said second shift register;

each of said first and second charge transfer devices including a like plurality of stages each including a plurality of charge storage sites, at each said stage of plurality of electrodes for receiving multi-phase clock pulses to transfer said analog signal samples along said charge transfer device;

means for applying to said stored sampled values of said second analog signal, a constant weighting coefficient equal to said constant d.c. reference level (B) applied to said first analog signal and for producing correspondingly amplitude weighted analog signals;

signal multiplier means for corresponding pairs of stages of said first and second charge transfer devices, for producing an output signal proportional to the product of first and second analog signal samples stored at the said corresponding stages of said first and second charge transfer devices, said signal multiplier means including first and second input electrodes electrically coupled to said corresponding stages of said first and second charge transfer devices for non-destructive detection of amplitudes of signal samples stored at said corresponding stages to apply analog pulse inputs to said first and second input electrodes; and

means for algebraically summing the outputs of said signal multiplication means with said amplitude weighted analog signals and for eliminating said d.c. reference level to produce an output signal.

17. The device of claim 16, wherein said charge transfer devices are charge coupled devices.

18. The device of claim 16, wherein said charge transfer devices are bucket brigade devices.

19. The device of claim 16, wherein at least one of said charge transfer devices is a charge coupled device and the or each remaining charge transfer device is a bucket brigade device.

20. Analog signal processing apparatus comprising:

a first charge transfer device analog shift register for receiving a first analog signal (V_S) and storing a plurality of sampled values of said first analog signal at charge storage sites of said shift register;

signal inverter means for receiving said first analog signal (V_S), said inverter means connected in parallel with said first charge transfer device;

a second charge transfer device analog shift register for receiving a second analog signal (V_G) having a predetermined non-zero d.c. reference level (B) to provide a unipolar input signal, and storing a plurality of sampled values of said unipolar input signal at charge storage sites of said second charge transfer device;

analog signal inverter means for receiving said first analog signal (V_S), said inverter being connected in parallel with said first charge transfer device;

a third charge transfer device analog shift register for receiving said inverted first analog signal from the output of said inverter means and for storing a plurality of sampled values of said inverted first analog signal at charge storage sites of said third charge transfer device;

means for applying to said stored sampled values of said inverted first analog signal, a constant weighting coefficient equal to said d.c. reference level (B) applied to said second analog signal and for producing correspondingly amplitude weighted analog signals;

each of said first, second, and third transfer devices including a like plurality of stages each including a plurality of charge storage sites, at each said charge storage site a plurality of electrodes for receiving multiphase clock pulses to transfer said signal samples along said charge transfer device;

analog signal multiplier means for corresponding pairs of stages of said first and second charge transfer devices, for producing an output signal proportional to the product of samples of said first analog signal and said unipolar signal stored at the said corresponding stages of said first and second charge transfer devices, said analog signal multiplier menas including first and second input electrodes electrically coupled to said corresponding stages of said first and second charge transfer devices for non-destructive detection of amplitudes of signal samples stored at said corresponding stages to apply analog pulse inputs to said first and second input electrodes; and

signal summation means for summing said amplitude weighted first analog signal samples and the output from said signal multiplier means algebraically to eliminate said d.c. reference level and said constant weighting coefficient.

21. The device of claim 20, wherein said charge transfer devices are charge coupled devices.

22. The device of claim 20, wherein said charge transfer devices are bucket brigade devices.

23. The device of claim 20, wherein at least one of said charge transfer devices comprises a charge coupled device and the or each remaining charge transfer device comprises a bucket brigade device.

24. A variable tap weight convolution filter comprising:

1. first and second charge transfer device analog shift registers including a plurality of stages each defining at least one charge storage site, said shift registers each having input means for receiving samples of respective first and second analog signals for storage at said storage sites;

each of said charge transfer devices further including a like plurality of electrodes for receiving multiphase clock pulses to transfer said analog signal samples along the stages of said charge transfer device;

2. for each storage of said first shift register and a corresponding stage of said second shift register, signal multiplication means comprising;

a. first and second insulated gate field effect transistors connected to define a source follower amplifier;

b. means coupling the gate of said first transistor to said stage of said first shift register for non-destructive detection of a signal sample stored at said stage and for applying a related gate bias voltage to said first transistor;

c. means coupling the gate of said second transistor to said corresponding stage of said second shift register for non-destructive sampling of a signal sample stored at said corresponding stage and to apply a related gate bias voltage to said second transistor; and

means connecting said source follower amplifiers between a supply voltage line and a common output line, whereby each said source follower amplifier produces an output signal proportional to the product of the amplitudes of said gate bias voltages applied thereto; and

3. signal summation means connected to said common output line for producing a convolution output signal.