Erasable programmable read-only memory

• US 3,938,108 A
• Filed: 02/03/1975
• Issued: 02/10/1976
• Est. Priority Date: 02/03/1975
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Perlegos, George, Salsbury, Phillip J.
• Primary Examiner(s): Cook, Daryl W.
• Application Number:
  US05/546,546
• Time in Patent Office: 372 Days
• Field of Search: 340/173 R, 340/173 SP, 307/238, 307/279, 307/304, 330/30 D
• US Class Current: 365/185.21
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 17/00 Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
• CPC Class Codes: H03K 19/01714 by bootstrapping, i.e. by positive feed-back
• CPC Class Codes: H03K 19/018507 Interface arrangements
• CPC Class Codes: H03K 19/09445 with active depletion transistors
• CPC Class Codes: H03K 5/003 Changing the DC level reinsertion of dc component of a television signal H04N5/16

Abstract

A TTL compatible erasable programmable read-only memory (PROM) which uses a single n-channel device having a floating gate for each memory cell. The entire memory including the periphery circuits, are disposed on a silicon substrate. Only a single externally generated high voltage input or "pin" is required for programming.

Claims

1. A read-only memory deployed on a doped silicon substrate comprising:

a first region on said substrate having a higher dopant level than said substrate;

a plurality of memory cells disposed in said first region, each of said cells including a floating gate for storing charge;

a plurality of buffers disposed on said substrate, spaced apart from said first region, for communicating signals to said memory cells, each of said buffers including a plurality of field-effect transistors having channels with a first level of dopant and at least one field-effect transistor having a channel with a second level of dopant wherein said saecond level of dopant is higher than said first level of dopant;

whereby said buffers act as level shifters to permit signals to be readily transmitted to said memory cells.

2. The memory defined by claim 1 wherein said first level of dopant is equal to the level of dopant of said doped silicon substrate.

3. The memory defined by claim 1 wherein in each of said buffers one of said transistors with said first level of dopant is connected on series with said transistor of said second level of dopant, and wherein the gate of said transistor with said second level of dopant received a buffered input signal referenced to external ground.

4. The memory defined in claim 3 wherein said one of said transistors with said first level of dopant has its gate coupled to a bootstrap circuit.

5. The memory defined in claim 1 wherein said buffers receive signals representative of an address, and wherein the output of each of said buffers is coupled to an address buffer comprising a plurality of transistors having channel with said first level of dopant and a plurality of transistors having channel with said second level of dopant.

6. The memory defined by claim 5 wherein the output from each of said address buffers comprises an output signal and its complement.

7. The memory defined in claim 6 including a plurality of decoders for deccoding an address, said decoders being coupled to said address buffers.

8. The memory defined in claim 7 including a terminal for receiving a programming signal for charging said floating gates of said memory cells.

9. The memory defined in claim 8 wherein said terminal is coupled to said cells through said decoders.

10. The memory defined in claim 9 wherein each of said decoders include a plurality of decoding transistors in series, said decoding transistors including gates coupled to receive said outputs of said address buffers.

11. The memory defined in claim 10 including bootstrapping means for bootstrapping said gates of said decoding transistors so that said decoding transistors will pass said programming signal.

12. The memory defined in claim 7 wherein said decoders are couples to said address buffers through a transfer gate such that a high voltage applied to said buffers is not transmitted to said address buffers.

13. The memory defined in claim 1 wherein the level of dopant of said first region is equal to said second level of dopant.

14. In a semiconductor memory disposed on a single silicon substrate and which includes a plurality of storage memory cells each of which has a floating gate for storing charge, a sense amplifier coupled to said cells comprising:

a first branch which includes a first load means and a first transistor, said first transistor being coupled to said storage memory cells;

a second branch coupled in parallel with said first branch, said second branch including a second load means and a second transistor;

a memory cell for establishing a reference potential, said memory cell including a floating gate, said memory cell being coupled to said second transistor;

whereby the reference potential provided by said memory cell establishes a level for said sense amplifier.

15. The amplifier defined by claim 14 wherein each of said storage memory cells and said memory cell for establishing a reference potential have the same dimensions.

16. The amplifier defined by claim 15 wherein said first and second load means each comprise load transistors.

17. The amplifier defined by claim 16 wherein said load transistor, said first and second transistors, said storage memory cells and said memory cell for establishing a reference potential all comprise n-channel devices.

18. A memory circuit having a plurality of floating gate MOS memory cells fabricated on a single silicon substrate comprising:

means for establishing a predetermined substrate voltage, said substrate voltage being coupled to each of said cells;

means for establishing an external reference voltage difference from said substrate voltage;

a a first buffer circuit including a first FET having a channel having a first predetermined dopant level, said first FET being biased with respect to said external reference voltage;

a level shifter having its input coupled to said first buffer circuit, said level shifter including a second FET having a channel having a second predetermined dopant level higher than said first predetermined dopant level, and a third FET, series-coupled to said second FET, having a channel having said first predetermined dopant level, said level shifter providing its output from said third FET;

a second buffer circuit coupled to the output of said level shifter, including a fourth FET having a channel having said first predetermined dopant level series-coupled to a fifth FET having a channel having said second predetermined dopant level, said second buffer circuit providing its output from said fifth FET said fifth FET being biased with respect to said substrate voltage.

19. The memory circuit of claim 18 further defined by the addition of a decoder circuit including a sixth FET having a channel having said first predetermined dopant level, the input of said decoder circuit being coupled to the output of said second buffer circuit and the output of said decoder circuit being coupled to each of said memory cells;

and

mean for coupling a programming signal to said decoder circuit through said sixth FET, said programming signal having a voltage level having an absolute value greater than either said substrate voltage or said external reference voltage.