Method for fabricating multilayer insulator-semiconductor memory apparatus

• US 3,964,085 A
• Filed: 08/18/1975
• Issued: 06/15/1976
• Est. Priority Date: 08/18/1975
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Inventors: Kahng, Dawon, Ligenza, Joseph Raymond, Lepselter, Martin Paul, La Bate, Ernest Edward
• Primary Examiner(s): Weiffenbach, Cameron K.
• Application Number:
  US05/605,312
• Time in Patent Office: 302 Days
• Field of Search: 427/85, 427/126, 427/255, 357/23, 357/24, 357/54
• US Class Current: 428/428
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10N 70/00 Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching integrated devices or assemblies of multiple devices H10N79/00

Abstract

An SI₁ I₂ M (semiconductor-insulator₁ -insulator₂ -metal) memory structure, containing an impurity such as tungsten concentrated in a region including the interface ("I₁ I₂ ") region between the I₁ and I₂ region, is fabricated by depositing an oxide of the impurity, such as tungsten trioxide, on the then exposed, I₁ layer prior to fabricating the I₂ layer. The oxide of the impurity, such as tungsten trioxide, can be advantageously deposited by means of reactive evaporation.

Claims

1. A semiconductor-insulator₁ -insulator₂ layered structure made by a process which includes the step of depositing an oxide of a metallic impurity on the then exposed surface of the insulator₁ layer, prior to the fabrication of the insulator₂ layer, in an amount yielding between about 10¹⁴ and 4 ×

10¹⁵ metallic impurity nuclei per square centimeter.

6. The method of claim 1 in which the oxide of the metallic impurity is tungsten trioxide and in which the step of depositing said tungsten trioxide is carried out in an ambient at a predetermined pressure of oxygen in which a heated tungsten body is located at a predetermined distance from said then exposed surface of the insulator₁ layer.

8. The method of claim 1 in which the metal is tungsten.

9. The method of claim 8 in which the surface concentration is between about 1 ×

10¹⁴ and 4 ×

10¹⁵ tungsten nuclei per square centimeter.

10. The method of claim 9 in which the surface concentration is between about 5 ×

10¹⁴ and 2 ×

10¹⁵ per square centimeter.

2. A semiconductor-insulator₁ -insulator₂ -metal layered structure made by a process including the steps of

a. forming the insulator₁ layer on the semiconductor layer;

b. depositing an oxide of a metallic impurity on the then exposed surface of the insulator₁ layer in an amount yielding between about 10¹⁴ and 4 ×

10¹⁵ nuclei of the metallic impurity per square centimeter;

followed by

c. forming the insulator₂ layer on the insulator₁ layer.

3. The structure of claim 2 in which the semiconductor is a silicon wafer, the insulator₁ layer is silicon dioxide grown on a major surface of the silicon wafer, and the metallic impurity is tungsten.

4. The structure of claim 2 in which the oxide of the metallic impurity is tungsten trioxide.

7. The method of claim 2 in which the surface concentration corresponds to between about 1 ×

10¹⁴ and 4 ×

10¹⁵ tungsten nuclei per square centimeter.

5. In a method for fabricating a memory apparatus comprising a semiconductor insulator₁ -insulator₂ -metal layered structure which contains metallic impurities in a predetermined molecularly dispersed surface concentration, without clumping which would form a Fermi level of the metallic impurities, in an interface insulator region (including the interface of the insulator layers), said impurities in a concentration supplying suitable states for the capture of electronic charges in said region, the step of depositing molecules of an oxide of the metallic impurity on the then exposed surface of the insulator₁ layer in an amount yielding said surface concentration of metallic impurities.

11. In a method for fabricating a semiconductor insulator₁ -insulator₂ -metal layered structure, in which the semiconductor is essentially silicon and in which the insulator₁ layer is essentially silicon dioxide, and in which a first interface insulator region (including the interface of the insulator layers) contains metal impurity nuclei which are dispersed in said insulator region without clumping which would form a Fermi level of the metal impurity, the step of depositing molecules of an oxide of the metal impurity on the then exposed surface of the insulator₁ layer to a surface concentration corresponding to between about 1 ×

10¹⁴ and about 4 ×

10¹⁵ of said metal impurity nuclei per square centimeter prior to depositing the insulator₂ layer.

12. The method of claim 11 in which the said surface concentration is between about 5 ×

10¹⁴ and 2 ×

10¹⁵ per square centimeter.

13. The method of claim 12 in which the metal impurity is tungsten.

14. The method of claim 11 in which the metal impurity is tungsten.

15. The method of claim 14 in which the oxide of the metal impurity is tungsten trioxide.

16. The product made by the process of claim 11.