Heart beat waveform monitoring apparatus

• US 3,978,856 A
• Filed: 03/20/1975
• Issued: 09/07/1976
• Est. Priority Date: 03/20/1975
• Status: Expired due to Term

• Current Assignee: Walter A. Michel
• Original Assignee: Walter A. Michel
• Inventors: Michel, Walter A.
• Primary Examiner(s): Kamm, William E.
• Application Number:
  US05/560,351
• Time in Patent Office: 537 Days
• Field of Search: 128/2.06 A, 128/2.06 B, 128/2.06 F, 128/2.06 R
• US Class Current: 600/516
• CPC Class Codes: A61B 5/364 Detecting abnormal ECG interval, e.g. extrasystoles, ectopic heartbeats
• CPC Class Codes: Y10S 128/901 Suppression of noise in electric signal

Abstract

Disclosed is a heart beat waveform monitoring apparatus for electronically analyzing the heart beat of an individual to recognize the unique characteristics of pre-ventricular contractions and other abnormalities of the heart beat rhythm, The device can detect and warn of the presence of tachycardia as well as prevent false indications of a "heart attack" due to noise. Logic circuits are provided to detect the characteristics of the abnormalities and to actuate an indicator.

Claims

1. Heart beat waveform monitoring apparatus for detecting heart beat waveforms by transducers secured to a patient and for analyzing the waveforms for abnormalities, the apparatus comprising:

first logic means for sensing presence of a QR rise in as heart beat waveform and producing a pulse responsive thereto;

second logic means for sensing presnce of an unusually wide QRS heart beat waveform and producing a pulse responsive thereto;

first AND gate means for receiving pulse signals from said first and said second logic means and passing an output pulse upon coincidence of said signals;

other logic means for detecting absence of a heart beat waveform following a first heart beat waveform and producing an output pulse responsive thereto;

second AND gate means for receiving output pulse signals from said first AND gate means and said other logic means; and

indicator means connected to said second AND gate means to be activated upon receiving a signal from said second AND gate means.

2. Heart beat waveform monitoring apparatus as in claim 1 wherein said first logic means is a rate logic circuit for receiving and analyzing a heart beat waveform and passing an output signal when a predetermined level of the QR rise is exceeded.

3. Apparatus as in claim 1 wherein output signals of said first logic means and said second logic means are stretched for possible coincidence at said first AND gate with a later output signal from said other logic means for causing passing of an output signal from said AND gate.

4. Heart beat waveform monitoring apparatus for detecting heart beat waveforms by transducers secured to a patient and for analyzing the waveforms for abnormalities, the apparatus comprising:

first logic means for sensing the presence of a QR rise in a heart beat waveform and producing a signal responsive thereto;

second logic means for sensing the presence of an unusually wide QRS heart beat waveform and producing a signal responsive thereto;

third logic means for sensing the absence of a pulse within a predetermined time following said signal generated by said first logic means, and passing a signal; and

And gate means for receiving said signals and passing an output signal when said signals are received in coincidence.

5. Apparatus as in claim 4 wherein said output signal of said first logic means is generated when a predetermined input signal strength is exceeded, and said output signal of said second logic means is generated when a wider than usual signal is received;

and including means stretching said output signals for possible coincidence at said AND gate with a later output signal from said third logic means for causing passing of an output signal from said AND gate.

6. Apparatus as in claim 4 including a fourth logic means for sensing a negative component in a heart beat waveform and passing an output signal to said AND gate when such component is detected.

7. Apparatus as in claim 4 including a second AND gate means for receiving said signals from said first logic means and said second logic means and passing an output signal when said signals are received in coincidence.