Capacitive voltage multiplier

• US 4,047,091 A
• Filed: 07/21/1976
• Issued: 09/06/1977
• Est. Priority Date: 07/21/1976
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Meyer, John E., Hutchines, Jimmy L.
• Primary Examiner(s): Shoop, William M.
• Time in patent office: 412 Days
• Field of Search: 321/15, 357/41, 357/51
• US Class Current: 363/60
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps for substrate bias voltage generators G05F3/205; for static stores G11C5/145, G11C16/06; charge pumping structures for internal polarisation H01L27/0222

Abstract

A voltage multiplier in which an n-phase circuit charges n-1 capacitors during the separate phases, then during the last or nth phase the capacitors are put in series to create n times the input voltage. MOS transistor devices are used to act as switches to charge a number of series connected capacitors. During a first phase of operation, the first in the series of capacitors is charged to a specific voltage to be multiplied by closing the MOS switches to place the voltage across the capacitor. During a next phase of operation, the first capacitor is disconnected by the switches and the next capacitor in series is charged to the input voltage. During successive phases of operation, successive capacitors are similarly charged. During the last phase of operation, the capacitors are connected in series with the voltage to be multiplied and are connected to an output capacitor. This places a total charge on the output capacitor which is equal to the sum of all the charges on the respective series connected capacitors plus the voltage to be multiplied. This results in an n+1 voltage multiplication wherein n is the number of series connected capacitors.

Claims

1. A voltage multiplier comprising:

a plurality of capacitors connected in series across the output pads of an integrated circuit chip;

a clock circuit providing multiphase voltage output;

means connecting the pads of said chip to MOS transistor switches;

means interconnecting said MOS switches to said clocking circuit such that during successive phases of operation said switches are closed in such a manner that the series connected capacitors are separately charged to the input voltage successively during each phase of said clock circuit; and

means operable during the final phase of operation of said clock for connecting an output capacitor to said input voltage and said series connected capacitors such that the voltage developed across the output capacitors is the sum of all the voltages across the series connected capacitors plus the input voltage.

2. A voltage multiplier comprising:

an integrated circuit chip having a first pad, a second pad, a third pad, and a fourth pad;

a clock circuit providing three outputs, a first phase, a second phase, and a third phase, wherein during each phase the respective output rises from a first voltage level to a second voltage level;

a first capacitor connected across said first and second pads;

a second capacitor connected across said second pad and said third pad;

a first and second MOS transistor connected source to drain between said second pad and said second phase output including means for energizing said first transistor during said first phase and said second transistor during said second phase whereby said first voltage level is applied to said second pad during said first phase and said second voltage level is applied to said second pad during said second phase;

a third MOS transistor connected between said third pad and said second voltage level including means for energizing said third transistor during said first phase for transferring said second voltage level to said third pad;

a fourth MOS transistor connected between said third and fourth pad operable during said third phase for connecting said third and fourth pads together;

a fifth MOS transistor connected between said first pad and said third phase output energizable during said second phase for transferring said first voltage level to said first pad;

whereby during said first phase of operation said second capacitor is charged to a voltage which is the difference between said first and second voltages applied to said second and third pads, respectively, through said first and third MOS transistors and whereby during said second phase said first capacitor is charged to a voltage which is the difference between said second and first voltges supplied by said second and fifth transistors, respectively, and whereby during said third phase of operation said third and fourth pads are connected together through said fourth MOS transistor to thereby apply the voltage on said capacitors to said fourth pad.

3. The combination according to claim 2 further comprising an output capacitor connected to said fourth pad and returned to said first voltage level to thereby provide for the transfer of the charge across said first and second capacitors to said output capacitor.