MOS buffer circuit

  • US 4,048,518 A
  • Filed: 12/27/1976
  • Issued: 09/13/1977
  • Est. Priority Date: 02/10/1976
  • Status: Expired due to Term
First Claim
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1. In an MOS inverter which includes an input transistor coupled in series with a load means, an improvement comprising:

  • a decoupling transistor coupled between said load means and said input transistor;

    the gate of said decoupling transistor being coupled to a controlled variable potential means for controlling the gate potential of said decoupling transistor in response to a change of voltage on the gate of said input transistor;

    whereby the voltage changes on the respective gates of said input transistor and said decoupling transistor together cause said decoupling transistor to rapidly decouple said input transistor from said load means, thereby allowing the output signal from said inverter to charge more quickly.

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