Pulse generator

• US 4,084,246 A
• Filed: 02/25/1977
• Issued: 04/11/1978
• Est. Priority Date: 10/18/1976
• Status: Expired due to Term

• Current Assignee: Perkinelmer Incorporated
• Original Assignee: Perkinelmer Incorporated
• Inventors: Schwartz, Arnold
• Primary Examiner(s): Gruber, Felix D.
• Application Number:
  US05/772,223
• Time in Patent Office: 410 Days
• Field of Search: 235/150.3, 235/151.3-151.35, 417/338, 137/87, 137/88, 137/98, 137/101.19, 328/38, 328/39, 328/48, 328/62, 328/180, 307/271, 307/225 R
• US Class Current: 702/46
• CPC Class Codes: F04B 13/02 of two or more fluids at the same time
• CPC Class Codes: F04B 49/06 Control using electricity regulating by means of floats actuating electric switches F04B49/04
• CPC Class Codes: G01N 2030/326 pumps
• CPC Class Codes: G01N 30/34 of fluid composition, e.g. gradient G01N30/36 takes precedence
• CPC Class Codes: H03K 23/66 with a variable counting base, e.g. by presetting or by adding or suppressing pulses
• CPC Class Codes: H03K 3/78 Generating a single train of pulses having a predetermined pattern, e.g. a predetermined number
• CPC Class Codes: Y10T 137/2529 With electrical controller

Abstract

A pulse generator for producing two output pulse trains A and B where the total number of pulses in both train A and B over a fixed time period remains a constant. The two pulse trains are derived from a master clock which gates a plurality of cascade connected synchronous decade rate multipliers. A selector is set either statically or dynamically to the value N where N is the number of pulses desired in one pulse train out of every M pulses produced by the master clock. A summing means is coupled to all the multipliers to produce a first intermediate pulse train with N pulses for every M clock pulses. A difference means is coupled to each multiplier and to the master clock to produce a pulse in a second intermediate pulse train every time a clock pulse occurs and a pulse in the first pulse train does not occur. A pulse counter is coupled to each intermediate pulse train output to produce two output pulse trains A and B each having a substantially constant pulse frequency.

Claims

1. A pulse generator for producing two pulse trains where the sum of pulses in both pulse trains in a constant over a fixed time period and the pulse rate of one train is selectable, the generator comprising, in combination:

a source of clock pulses with one clock pulse occurring per clock cycle;

a plurality of selector means each selectively providing a unique signal representative of a decimal digit correlated to the pulse rate of one pulse train;

a plurality of synchronous decade rate multipliers each coupled to said source of clock pulses and to one selector means to receive unique signals therefrom, said decade rate multipliers being connected in cascade so that the first decade rate multiplier is operative during each clock cycle and capable of producing an output pulse during nine out of every ten clock cycles, each successive decade rate multiplier is operative during only the one clock cycle that the previous rate multiplier cannot produce an output pulse, each said decade rate multiplier producing X pulses at its output for each ten clock cycles that it is operative where X corresponds to the setting of the selector means coupled thereto;

summing means responsive to the output pulses from each said decade rate multiplier to produce a pulse in a first intermediate pulse train for each output pulse from any decade rate multiplier;

difference means responsive to said clock pulses and the output from each said decade rate multiplier to produce a second intermediate pulse train having a pulse whenever a clock pulse occurs in the absence of an output pulse from any said decade rate multiplier; and

a first pulse counter responsive to said first intermediate pulse train and a second pulse counter responsive to said second intermediate pulse train, each said pulse counter being operative to produce one output pulse in a pulse train for every N intermediate pulses input thereto, the output of said first pulse counter comprises a first output pulse train and the output of said second pulse counter comprises a second output pulse train, where N is the whole decimal number.

2. The pulse generator of claim 1 wherein the rate of said source of clock pulses is adjustable so that the constant sum of said two output pulse trains is adjustable.

3. The pulse generator of claim 1 wherein each said selector means includes means to actuate a plurality of output lines to place a binary coded signal thereon corresponding to the digit to which it is set.

4. The pulse generator of claim 1 wherein said difference means comprises, in combination:

a first inverter to invert said clock pulses to produce inverted clock pulses; and

a NAND gate responsive to said first inverter and to the output pulses from each said decade rate multiplier to produce output pulses comprising the inverted said second intermediate pulse train.

5. The pulse generator of claim 1 additionally including pump means responsive to said first output pulse train to pump a first fluid at a rate correlated to the frequency of pulses in said first output pulse train and including means responsive to said second output pulse train to pump a second fluid at a rate correlated to the frequency of pulses in said second output pulse train.

6. The pulse generator of claim 1 wherein said plurality of selector means includes means responsive to changes in at least one external condition to dynamically change the decimal digit signal produced thereby.

7. A control circuit for controlling the rate of flow of two fluids so that the total rate of flow of the two fluids is a constant while the ratio of one fluid flow rate to the other is adjustable, the control circuit comprising, in combination:

a pulse generator producing clock pulses at an adjustable rate wherein the clock pulse rate is correlated to the total flow rate of the two fluids;

selector means for producing signals representative of a plurality of decimal digits correlated to the flow rate of one fluid;

a plurality of synchronous decade rate multipliers connected in cascade and responsive to said pulse generator and said selector means, each decade rate multiplier producing output pulses correlated to the signals representative of one said decimal digit;

summing means responsive to each output from each said decade rate multiplier to produce a first intermediate pulse train with one pulse for each pulse input to said summing means;

difference means responsive to said clock pulses and each said decade rate multiplier to produce a second intermediate pulse train having a pulse occurring at the time each clock pulse occurs in the absence of an output pulse from any said rate multiplier;

first spectral purifying means to produce one pulse in a first train of output pulses for every N pulses in said first intermediate pulse train where N is a whole decimal number;

second spectral purifying means to produce one pulse in a second train of output pulses for every N pulse in said second intermediate pulse train;

first pump means responsive to said first train of output pulses to pump a first fluid at a rate proportional to the pulse rate of said first train of output pulses; and

second pump means responsive to said second train of output pulses to pump a second fluid at a rate proportional to the pulse rate of said second train of output pulses.

8. The control circuit of claim 7 wherein said summing circuit logically ORs the output pulses from each said rate multiplier to produce said first intermediate pulse train.

9. The control circuit of claim 7 wherein said difference means comprises:

an inverter responsive to said clock pulses to produce inverted clock pulses;

a NAND gate responsive to the output pulses from each said rate multiplier and to said inverse clock pulses to produce an inverse second intermediate pulse string; and

an inverter responsive to said inverted second intermediate pulse string to produce said second intermediate pulse string.

10. The control circuit of claim 7 wherein said first and said second spectral purifying means each comprise a pulse divider circuit for dividing the pulse train input thereto by N.

11. The control circuit of claim 7 wherein said selector means includes means responsive to an external condition to dynamically produce signals representative of that changing condition which comprises said signals representative of a plurality of decimal digits.

12. The control circuit of claim 7 additionally including a second selector means to produce a unique signal for each digit in a second number Y having q digits therein correlated to adjustment of the flow rate of said first pump means;

a second plurality of decade rate multipliers coupled to said summing means and to said second selector means to produce modified first intermediate pulse train having Y pulses therein for every 10^q pulses input thereto, said modified first intermediate pulse train being coupled to said first spectral purifying means in place of said first intermediate pulse train.

13. The control circuit of claim 12 additionally including a further selector means to produce a unique signal for each digit in a number Z having q digits therein correlated to adjustment of the rate of flow of said second pump means;

and

a further plurality of decade rate multipliers coupled to said difference means and to said further selector means to produce a modified second intermediate pulse train having Z pulses therein for every 10^q pulses input thereto, said modified second intermediate pulse train being coupled to said second spectral purifying means in place of said intermediate pulse train.

14. The control circuit of claim 7 additionally including a further selector means to produce a unique signal for each digit in a number Z having q digits therein correlated to adjustment of the rate of flow of said second pump means;

and

a further plurality of decade rate multipliers coupled to said difference means and to said further selector means to produce a modified second intermediate pulse train having Z pulses therein for every 10^q pulses input thereto, said modified second intermediate pulse train being coupled to said second spectral purifying means in place of said second intermediate pulse train.

15. A pulse generator for producing two pulse trains A and B comprising, in combination:

a clock pulse generator for producing clock pulses at a rate QF where Q is a number and F is a pulse rate;

P selector means for selecting a number N where P corresponds to the number of digits in the number N where N₁ is the most significant digit and N_p is the least significant digit;

P pulse rate changing circuits coupled in cascade where each said pulse rate changing circuit is coupled to said clock pulse generator and to one said selector means, each successive pulse rate changing circuit producing N_q pulses for every 10^q clock pulses where q corresponds to the digit significance of the number N where q=1 for the most significant digit and q=P for the least significant digit;

means for summing the pulses produced at each said pulse rate changing circuit to produce a first output pulse train wherein the number of pulses produced thereby equals N for every 10^p clock pulses;

difference means responsive to said clock pulse generator and each said pulse rate changing circuit to produce a second output pulse train with (10^P -N) pulses for every 10^P clock pulses;

first division means to divide said first output pulse train by Q to produce pulse train A with an output frequency f_A equal to F ×

N; and

second division means to divide said second output pulse train 10^P by Q to produce pulse train B with an output frequency f_B equal to F [1 - (N/10^p)].

16. The pulse generator of claim 15 wherein said clock pulse generator includes means to vary the rate of pulses produced thereby.

17. The pulse generator of claim 15 wherein said summing means comprises a circuit to produce a pulse for each pulse produced by any said pulse rate changing circuit.

18. The pulse generator of claim 15 wherein said difference means includes:

an inverter responsive to said clock pulse generator to produce inverted clock pulses;

a NAND gate responsive to said inverted clock pulses and to said pulses from each said pulse rate changing circuit for producing a pulse whenever a pulse is not produced at any pulse rate changing circuit at the time of a pulse from said clock generator.

19. The pulse generator of claim 15 wherein said difference means includes a circuit to produce a pulse at the time of a clock pulse if no pulse is produced at that time by any said pulse rate changing circuit.

20. The pulse generator of claim 15 additionally including pump means responsive to pulse train A to pump a fluid at a rate proportional to the frequency f_A of pulses in pulse train A.

21. The pulse generator of claim 15 additionally including pump means responsive to pulse train B to pump a fluid at a rate proportional to the frequency f_B of pulses in pulse train B.

22. The generator of claim 15 additionally including:

first pump means responsive to pulse train A to pump a first fluid at a rate proportional to the frequency f_A of pulses in pulse train A; and

second pump means responsive to pulse train B to pump a second fluid at a rate proportional to the frequency f_B of pulse train B.

23. The pulse generator of claim 22 wherein said clock pulse generator includes means to vary the rate of pulses produced thereby to adjust the total flow rate of said first and said second fluid.

24. The pulse generator of claim 15 wherein said P selector means includes means responsive dynamically to an external condition to vary the number N in response to changes in said external condition.

25. The pulse generator of claim 15 additionally including an adjustable pulse division means for selectively producing from said first output pulse train a modified first output pulse train having no more than N pulses every 10^P clock pulses, said modified first output pulse train being coupled to said first division means in place of said first output pulse train.

26. The pulse generator of claim 15 additionally including an adjustable pulse division means for selectively producing from said second output pulse train a modified second output pulse train having no more than (10^P -N) pulses every 10^p clock pulses, said modified second output pulse train being coupled to said second division means in place of said second output pulse train.

27. A pulse generator for producing two pulse trains suitable for controlling the operation of two pumps so that the total flow rate of both pumps remains a constant while the rate of one pump is selectable, the generator comprising, in combination:

a source of clock pulses with one clock pulse occurring per clock cycle;

a plurality of selector means each selectively providing an unique signal representative of a decimal digit correlated to a first pulse rate;

a plurality of first decade rate multipliers each coupled to said source of clock pulses and to one selector means to receive unique signals therefrom, said first decade rate multipliers being connected in cascade so that the first decade rate multiplier is operative during each clock cycle and capable of producing an output pulse during nine out of every ten clock cycles, each successive first decade rate multiplier is operative during only the one clock cycle that the previous first decade rate multiplier cannot produce an output pulse, each said first decade rate multiplier being capable of producing X pulses at its output for each ten clock cycles that it is operative where X corresponds to the setting of the selector means coupled thereto;

summing means responsive to the output pulses from each said first decade rate multiplier to produce a pulse in a first intermediate pulse train for each output pulse from each first decade rate multiplier;

difference means responsive to each said clock pulse and said output pulses from each first decade rate multiplier to produce a second intermediate pulse train having a pulse during each clock cycle occurring in the absence of a pulse from any said first decade rate multiplier;

at least one second decade rate multiplier coupled to first intermediate pulse train and to a selector means for each said second decade rate multiplier to receive unique signals therefrom, said second decade rate multipliers producing a third intermediate pulse train having Y pulses for each 10^p pulses in the first intermediate pulse train where Y corresponds to the setting of the selector means coupled to said second decade rate multipliers and p corresponds to the number of said second decade rate multipliers; and

at least one third decade rate multiplier, each coupled to said second intermediate pulse train and to a selector means to receive unique signals therefrom, said third decade rate multipliers producing a fourth intermediate pulse train having Z pulses for every 10^q pulses in said second intermediate pulse train where Z corresponds to the setting of the selector means coupled to said third decade rate multiplier and where q equals the number of third rate multipliers.

28. The pulse generator of claim 27 additionally including a first pulse counter responsive to said third intermediate pulse train and a second pulse counter responsive to said fourth intermediate pulse train, each said pulse counter producing one pulse at its output for each N pulses input thereto where N is a whole decimal number.

29. The pulse generator of claim 28 additionally including a first pump means responsive to said first pulse counter and a second pump means responsive to said second pulse counter, each said pump means being operative to pump a fluid at a flow rate related to the rate of pulses received from the pulse counter coupled thereto.

30. The pulse generator of claim 27 wherein said source of clock pulses is adjustable to produce clock pulses at an adjustable rate.