Photovoltaic cell array

• US 4,127,424 A
• Filed: 08/26/1977
• Issued: 11/28/1978
• Est. Priority Date: 12/06/1976
• Status: Expired due to Term

• Current Assignee: S.E.S. Co., Ltd.
• Original Assignee: S.E.S. Co., Ltd.
• Inventors: Ullery, Lee R. Jr.
• Primary Examiner(s): Mack, John H.
• Assistant Examiner(s): Weisstuch, Aaron
• Application Number:
  US05/827,927
• Time in Patent Office: 459 Days
• Field of Search: 136/89 P, 136/89 CD, 136/89 CC, 136/89 PC, 136/89 TF, 357/67
• US Class Current: 136/244
• CPC Class Codes: H01L 31/046 PV modules composed of a plurality of thin film solar cells deposited on the same substrate
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

In a photovoltaic cell which comprises: a substrate, a bottom electrode, a first layer of cadmium sulfide, a second layer of cuprous sulfide forming a barrier junction with said first layer and a top electrode, the improvement wherein said substrate is an insulative ceramic material and the bottom electrode is a conductive ceramic layer fused to said substrate. Said conductive layer is optionally coated with a metal having a high electrical conductivity.

Claims

1. In an integrated array of connected, thin film, photovoltaic cells comprising:

a substrate of electrically insulative material;

a plurality of thin film photovoltaic cells integrally united to a major surface of said substrate in a spaced-apart relationship, each of said cells comprising;

an electrically conductive bottom electrode united to said major surface of said substrate;

a film of first semiconductor material of one type conductivity covering and overlapping all but a portion adjacent an edge of said bottom electrode;

a film of second semiconductor material of opposite type conductivity and forming a p-n junction with the first semiconductor material and;

a top electrode, in contact with said second semiconductor material and which allows radiant energy to pass into the second semiconductor material, selected ones of said top and bottom electrodes of one cell being connected to selected top and bottom electrodes of adjacent cells to connect said cells in a series or parallel arrangement;

the improvement wherein said substrate comprises an insulative ceramic and said bottom electrode comprises an electrically conductive ceramic united to said major surface of said substrate.

2. The integrated array of claim 1 wherein said substrate comprises sheet metal coated at least on one side with a thin layer of insulating ceramic.

3. The integrated array of claim 1 wherein the bottom electrode comprises from about 15 to about 85 percent by weight of a metal, from about 5 to about 50 percent by weight of ceramic material and from about 5 to about 60 percent by weight of a metal oxide.

4. The integrated array of claim 3 wherein the bottom electrode comprises from about 70 to about 85 percent by weight of the metal, from about 10 to about 20 percent by weight of the ceramic material and from about 5 to about 10 percent by weight of the metal oxide.

5. The integrated array of claim 3 wherein the bottom electrode comprises from about 15 to about 70 percent by weight of the metal.

6. The integrated array of claim 5, wherein said bottom electrode comprises copper and cuprous oxide, having deposited thereon a layer of copper and having further deposited thereon a layer of zinc, said first semiconductor material is cadmium sulfide and said second semiconductor material is cuprous sulfide.

7. The integrated array of claim 6, wherein the substrate comprises sheet metal coated on at least one side with a thin layer of insulating ceramic.

8. The integrated array of claim 3, wherein said conductive ceramic is coated with at least one metal layer, one of which makes an ohmic contact with the first semiconductor material.

9. The integrated array of claim 6, wherein said bottom electrode comprises copper and cuprous oxide, said metal coating is zinc, said first semiconductor material is cadmium sulfide and said second semiconductor material is cuprous sulfide.

10. The integrated array of claim 7, wherein the substrate comprises sheet metal coated on at least one side with a thin layer of insulating ceramic.