Data processing apparatus for highly parallel execution of data structure operations

• US 4,149,240 A
• Filed: 06/14/1976
• Issued: 04/10/1979
• Est. Priority Date: 03/29/1974
• Status: Expired due to Term

• Current Assignee: Dataflow Computer Corporation, David P. Misunas
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Dennis, Jack B., Misunas, David P.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Rhoads, Jan E.
• Application Number:
  US05/695,721
• Time in Patent Office: 1,030 Days
• Field of Search: 364/200, 364/900, 179/15 AL, 179/15 AT, 179/15 BA, 179/15 BV, 179/18 ES
• US Class Current: 712/25
• CPC Class Codes: G06F 9/4494 data driven

Abstract

A digital computer may be structured in two separate sections, one of which performs the execution of arithmetic and conditional instructions, and the other which contains and performs operations upon data structures. The organization of the structure processing section of a digital computer is described herein. The structure processing section maintains data structures represented as acyclic directed graphs and is viewed as a functional unit by the instruction processing section; that is, instructions specifying structure operations are sent to the section, and any resulting values are returned to the instruction processing section. The organization of the structure processing section permits the simultaneous processing of many structure operations.

Claims

1. A digital data processor comprising:

(a) structure memory means for holding at least a record of structure nodes, said structure memory means containing a plurality of structure cells, each of said structure cells either holding one structure node of said record of structure nodes or being empty, and each structure cell having a unique index;

(b) structure operation means for managing signals in the execution of data structure operations, said data structure operations comprising read and write operations on the structure nodes comprising said record of structure nodes held in said structure memory means;

(c) status means for managing signals in maintaining a reference count associated with each structure node of said record of structure nodes held in said structure memory means, said reference count designating the number of references to its associated structure node existing in said digital data processor;

(d) identity means for managing signals in the execution of identity operations;

(e) instruction processing means for managing signals in the execution of instructions of a program and transmitting signals representing first information packets to said structure operation means and signals representing second information packets to said status means, said signals representing first information packets comprising signals representing read and write operations to be executed on said structure nodes of said record of structure nodes contained in said structure memory means and said signals representing second information packets consisting of signals representing operations necessary for maintenance of said reference count associated with each structure node of said record of structure nodes maintained in said structure memory means;

(f) distribution means operatively connected between said structure operation means and said structure memory means for concurrently transmitting signals representing a plurality of third information packets from said structure operation means and said identity means to said structure memory means, each of said signals representing third information packets consisting of signals representing an operation to be performed on a structure node of said record of structure nodes, together with all required operands;

(g) first arbitration means operatively connected between said structure memory means and said instruction processing means for concurrently transmitting signals representing a plurality of fourth information packets from said structure memory means to said instruction processing means, said signals representing fourth information packets consisting of signals representing data values resulting from execution of operations specified in said signals representing third information packets received by said structure memory means;

(h) second arbitration means operatively connected between said structure memory means and said status means for concurrently transmitting signals representing a plurality of fifth information packets from said structure memory means to said status means, said signals representing fifth information packets consisting of signals representing operations necessary for maintenance of said reference count associated with each structure node of said record of structure nodes maintained in said structure memory means; and

(i) third arbitration means operatively connected between said structure memory means and said identity means for concurrently transmitting signals representing a plurality of sixth information packets from said structure memory means to said identity means, said signals representing sixth information packets consisting of signals representing operations to be performed on said structure nodes of said record of structure nodes contained in said structure memory means, together with all required operands.

2. The digital data processor of claim 1 wherein said structure memory means includes a plurality of structure cells, each of said structure cells having registers, each of said registers consisting of means for holding information records.

3. The digital data processor of claim 2 wherein each of said information records includes data items and descriptors.

4. The digital data processor of claim 3 wherein each of said data items consists of means for holding either data values or unique structure cell address indices.

5. The digital data processor of claim 3 wherein each of said descriptors includes selector means and register status means.

6. The digital data processor of claim 5 wherein each of said selector means consists of means for distinguishing a data item contained in an information record from said data items contained in other of said information records of said structure cell.

7. The digital data processor of claim 5 wherein each of said register status means consists of means for designating whether said information records are empty or said information records are full and said data items contained in said information records are unique structure cell address indices or data values.

8. The digital data processor of claim 2 wherein said signals representing third information packets are received by said structure memory means from said distribution means, said signals representing third information packets containing unique structure cell address indices and instructions consisting of functional specifications, destination specifications, and all relevant operands;

said signals representing fourth information packets directed from said structure memory means to said first arbitration means include destination specifications and data values;

said signals representing fifth information packets directed from said structure memory means to said second arbitration means include unique structure cell address indices and commands; and

said signals representing sixth information packets directed from said structure memory means to said third arbitration means include unique structure cell address indices and instructions, each instruction consisting of a functional specification, destination specifications, and all relevant operands.

9. The digital data processor of claim 1 wherein said structure operation means consists of means for interpreting said signals representing first information packets received from said instruction processing means and means for sending, in response to said signals representing first information packets received from said instruction processing means, signals representing seventh information packets to said status means and signals representing third information packets to said distribution means for conveyance to said structure memory means, said signals representing seventh information packets consisting of signals representing operations necessary for the maintenance of the reference count associated with each structure node of said record of structure nodes maintained in said structure memory means and signals requesting unique structure cell indices of structure cells which are empty.

10. The digital data processor of claim 9 wherein said signals representing first information packets are received by said structure operation means from said instruction processing means, said signals representing first information packets containing unique structure cell address indices and instructions, each instruction consisting of a functional specification, destination specifications, and all relevant operands;

signals representing eighth information packets are received by said structure operation means from said status means, said signals representing eighth information packets containing unique structure cell address indices;

said signals representing third information packets directed from said structure operation means to said distribution means include unique structure cell address indices and instructions, each instruction consisting of a functional specification, destination specifications, and all relevant operands; and

said signals representing seventh information packets directed from said structure operation means to said status means include unique structure cell address indices and commands.

11. The digital data processor of claim 2 wherein said status means consists of means for maintaining reference count records for a plurality of said structure cells in said structure memory means and means for maintaining a list of the unique structure cell indices associated with empty structure cells in said structure memory means.

12. The digital data processor of claim 11 wherein each of said reference count records consists of means for designating the number of said registers comprising said structure cells in said structure memory which contain data records consisting of the unique index of said structure cell associated with said reference count record and the number of references existing in said instruction processing means to said structure cell associated with said reference count record.

13. The digital data processor of claim 12 wherein said reference count record holds an integer value which is incremented or decremented in response to said signals representing fifth information packets received from said second arbitration means, said signals representing second information packets received from said instruction processing means, and said signals representing seventh information packets received from said structure operation means, and said reference count record becoming zero causing the unique structure cell index associated with said reference count record to be placed on the list of unique structure cell indices associated with structure cells which are empty.

14. The digital data processor of claim 12 wherein said signals representing fifth information packets are received by said status means from said second arbitration means, said signals representing second information packets are received by said status means from said instruction processing means, and said signals representing seventh information packets are received by said status means from said structure operation means, said signals representing fifth, second, and seventh information packets consisting of signals representing unique structure cell address indices and up or dwn commands specifying the incrementing or decrementing of said reference count records and getid commands requesting unique structure identifiers, and said signals representing eighth information packets directed from said status means to said structure operation means include destination specifications and unique structure cell address indices, where said signals representing eighth information packets are transmitted in response to said signals representing seventh information packets specifying getid operations.

15. The digital data processor of claim 1 wherein said identity means transmits said signals representing fifth information packets received from said third arbitration means as signals representing third information packets to said distribution means.

16. The digital data processor of claim 15 wherein said signals representing fifth information packets are received by said identity means from said second arbitration means, said signals representing fifth information packets consisting of signals representing unique structure cell address indices and instructions, each instruction consisting of a functional specification, destination specifications, and all relevant operands, and said signals representing third information packets directed from said identity means to said distribution means consisting of signals representing unique structure cell address indices and instructions, each instruction consisting of a functional specification, destination specifications, and all relevant operands.

17. The digital data processor of claim 1 wherein a plurality of said signals representing third information packets are transmitted simultaneously by said distribution means and said signals representing third information packets consist of signals representing a unique structure cell address index and an instruction consisting of a function specification, destination specifications, and all relevant operands, said unique structure cell address index specifying a path through said distribution means to a destination structure cell in said structure memory means.

18. The digital data processor of claim 1 wherein a plurality of said signals representing fourth information packets are transmitted simultaneously by said first arbitration means and said signals representing fourth information packets consist of signals representing a destination specification and a data item, wherein said destination specification designates a destination for said information packet within said instruction processing means.

19. The digital data processor of claim 1 wherein a plurality of said signals representing fourth information packets are transmitted simultaneously by said second arbitration means and said signals representing fourth information packets consist of signals representing a unique structure cell address index and a command, said command designating an operation to be performed in said status means.

20. The digital data processor of claim 1 wherein a plurality of said signals representing fifth information packets are transmitted simultaneously by said third arbitration means and said signals representing fifth information packets consist of signals representing a unique structure cell address index and an instruction consisting of a function specification, destination specifications, and all relevant operands, said unique structure cell address index specifying a path through said distribution means to a destination structure cell in said structure memory means.