Digital clock recovery circuit

• US 4,151,485 A
• Filed: 11/21/1977
• Issued: 04/24/1979
• Est. Priority Date: 11/21/1977
• Status: Expired due to Term

• Current Assignee: Rockwell International Corporation
• Original Assignee: Rockwell International Corporation
• Inventors: LaFratta, Laurence A.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US05/853,149
• Time in Patent Office: 519 Days
• Field of Search: 331/1 A, 331/8, 331/10-12, 331/18, 331/25, 331/27
• US Class Current: 331/1.00A
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/148 said digital means comprising a counter or a divider
• CPC Class Codes: H03L 7/189 comprising a D/A converter for generating a coarse tuning voltage
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A digital clock signal tracks a pulse stream data signal by developing two phase-lock restorative voltages through a phase-locked loop circuit which control the loop VCO that generates the clock signal, one voltage, designated as fine, being developed through a digital up/down counter and a digital/analog converter whenever the phase difference between the two signals exceeds a first threshold, and the second voltage, designated as coarse being generated by combining with the fine voltage a voltage to reduce or increase its value before application to the VCO so that the altered control voltage rapidly restores phase-lock whenever the phase difference exceeds a second threshold greater than that of the first.

Claims

1. A clock recovery circuit for generating a clock signal which tracks a pulse stream data signal, comprising:

voltage controlled oscillator means for providing the clock signal;

phase difference means for monitoring the phase difference between the clock and data signals and providing first and second signals whenever the phase difference exceeds first and second thresholds, respectively, said second threshold being greater than said first and said second signal being terminated coincident with the termination of said first signal;

relative phase means for comparing the relative phase of the clock and data signals to provide a third signal indicative of their relative positions in time;

an up/down digital counter responsive to said first signal for changing its count, the counting direction being determined by said third signal;

a digital/analog converter connected to the output of said digital counter;

coarse control circuit means responsive to said second signal for providing a voltage to be combined with the output of said converter to lower or raise its magnitude as determined by said third signal;

circuit means for applying said combined output to said oscillator means so as to reduce the aforesaid phase difference.

2. The clock recovery circuit of claim 1 wherein said combined output has a bilevel mangitude, each level corresponding to one of the voltage limits of the operating range for said voltage controlled oscillator means.

3. The clock recovery circuit of claim 1 wherein said phase difference means comprises two D-type flip-flops, each for providing said first and second output signals.

4. The clock recovery circuit of claim 1 including a data fade detector for detecting the absence of a data signal and inhibiting said coarse control means in response thereto.

5. A method for generating a clock signal which tracks a pulse stream data signal, comprising:

generating a clock signal whose frequency is a function of a control voltage;

monitoring the phase difference between the clock and data signals to provide first and second signals whenever the phase difference exceeds first and second thresholds, respectively, said second threshold being greater than said first threshold and said second signal being terminated coincident with the termination of said first signal;

comparing the relative phase of the clock and data signals to provide a third signal indicative of their relative positions in time;

changing a digital count in response to said first signal, the counting direction being determined by said third signal;

converting the digital count to an analog voltage;

generating a voltage to be combined with said analog voltage to lower or raise its magnitude as determined by said third signal, and

applying the combined voltage as said control voltage to reduce the aforesaid phase difference.

6. The method of claim 5 wherein said combined output has a bilevel magnitude, each level corresponding to one of the voltage limits of the operating range of said control voltage.

7. In combination with a digital phase locked-loop circuit having a voltage controlled oscillator for providing a clock signal that tracks a pulse stream data signal under the control of the output of an up/down digital counter via a digital/analog converter and a phase detector for effecting a count change in the counter whenever the phase difference between the data and clock signals exceeds a first threshold, the direction of change being such as to reduce the aforesaid phase difference, a coarse control circuit comprising:

means for generating and combining with the converter output a voltage to reduce the phase difference whenever it exceeds a second threshold which is greater than the first threshold;

means for applying the combined voltage to the oscillator, and

means for terminating the generated voltage whenever the aforesaid phase difference falls below the first threshold.

8. The coarse control circuit of claim 7 wherein said combined voltage has a bilevel magnitude, each level corresponding to one of the limits of the operating range for the voltage controlled oscillator.

9. The coarse control circuit of claim 7 including a data fade detector for detecting the absence of a data signal and inhibiting the generating means in response thereto.