Digital phase detector and method
First Claim
1. A digital phase detector, comprising:
- a hard limiter, operably connected to an incoming signal of known frequency to produce a signal square wave having said frequency;
a reference generator, said generator producing a reference square wave and a 90°
phase shifted reference square wave, each having said known frequency;
a first logic element operably connected to produce a multiplicative output from the input of said signal square wave and said reference square wave;
a second logic element operably connected to produce a multiplicative output from the input of said signal square wave and said 90°
phase shifted reference square wave;
a phase modulated clock;
a first counter operably connected to count said phase modulated clock under control of the output from said first logic element;
a second counter operably connected to count said phase modulated clock under control of the output from said second logic element; and
a digital processor, said processor operably connected to compute a phase estimate from the counts registered by said first and second counters.
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Abstract
A digital phase detector includes a hard limiter which transforms an incoming signal of known frequency into a binary signal at the same frequency. A reference generator produces two binary references at the signal frequency, one reference shifted 90° in phase with respect to the other. The binary signal is exclusive-ORed with each reference and the exclusive-OR outputs therefrom control two counters, the counters thereby registering counts analogous to trigonometric functions of the signal phase angle. A phase modulated clock drives the counters, the phase modulation feature permitting a correction factor to be incorporated in order to cancel the error introduced by the quantized nature of the digital computations involved.
33 Citations
17 Claims
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1. A digital phase detector, comprising:
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a hard limiter, operably connected to an incoming signal of known frequency to produce a signal square wave having said frequency; a reference generator, said generator producing a reference square wave and a 90°
phase shifted reference square wave, each having said known frequency;a first logic element operably connected to produce a multiplicative output from the input of said signal square wave and said reference square wave; a second logic element operably connected to produce a multiplicative output from the input of said signal square wave and said 90°
phase shifted reference square wave;a phase modulated clock; a first counter operably connected to count said phase modulated clock under control of the output from said first logic element; a second counter operably connected to count said phase modulated clock under control of the output from said second logic element; and a digital processor, said processor operably connected to compute a phase estimate from the counts registered by said first and second counters. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A phase modulated clock modulated according to a predetermined modulation function for use in a digital phase detector, said clock comprising:
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a read only memory loaded with clock rate correction factors, said correction factors controlling the placement of each phase modulated clock pulse to minimize the phase error between the modulated clock phase and the phase according to the modulation function; a high speed clock; a programmable divider operably connected to said read only memory and said high speed clock, for generating the phase modulated clock pulses by counting high speed clock pulses in a varying rate according to said clock rate correction factors; and a fixed divider operably connected to said programmable divider and said read only memory, said fixed divider addressing the appropriate location in said read only memory at each output pulse from said programmable divider. - View Dependent Claims (13)
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14. A method of detecting a phase difference, comprising the steps of:
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hard limiting an incoming signal of known frequency; combining the signal with a reference square wave at the same frequency to produce a first multiplicative output; combining the signal with a 90°
phase shifted reference square wave at the same frequency to produce a second multiplicative output;gating a phase modulated clock by said first and second multiplicative outputs to generate first and second gated phase modulated clock pulses, respectively; separately counting said gated phase modulated clock pulses; and applying an arctangent function to the ratio of said counts. - View Dependent Claims (15, 16, 17)
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Specification