Digital delay line apparatus

• US 4,181,975 A
• Filed: 07/10/1978
• Issued: 01/01/1980
• Est. Priority Date: 07/10/1978
• Status: Expired due to Term

• Current Assignee: Alcatel Network Systems India Limited (Nokia Corporation)
• Original Assignee: Rockwell International Corporation
• Inventors: Jenkins, James R.
• Primary Examiner(s): Boudreau, Leo H.
• Application Number:
  US05/923,262
• Time in Patent Office: 540 Days
• Field of Search: 364/900, 307/208, 307/232, 307/262, 307/293, 328/129, 328/155, 328/133
• US Class Current: 370/517
• CPC Class Codes: H03H 17/0009 Time-delay networks

Abstract

Apparatus is illustrated for delaying in increments of infinitesimally small electrical angles the data bits in a data stream using an addressable elastic buffer which is addressed by a phase lock loop used to compare the output data with a reference. The comparison can be as a result of a frame detection puslse or any other suitable characteristic of the data being delayed.

Claims

1. Apparatus for providing continuous delay adjustment of a digital delay line comprising, in combination:

first means for supplying data bit stream signals;

second means for supplying clock bit stream signals;

elastic store means, connected to said first and said second means for receiving signals therefrom, said elastic store means operating to consecutively store received data bits at times dictated by clock bit signals and to parallel output stored data bits;

multiplex means, including address input means, data input means and data output means, for outputting at least one addressed input bit upon command;

means connecting said elastic store means to said data input means of said multiplex means for supplying data bits thereto;

phase lock loop means, including first and second signal input means and command signal output means, for altering command signals in accordance with deviation of phasing of signals applied at said first and second signal input means from a desired value;

means connecting said data output means of said multiplex means to said first signal input means of said phase lock loop means;

means for supplying signals of variable phase, with respect to the phase of data signals supplied by said first means, to said second signal input means of said phase lock loop means; and

means connecting said command signal output means of said phase lock loop means to said address input means of said multiplex means for supplying signals thereto.

2. The method of delaying a digital data bit stream comprising the steps of:

storing incoming data bit in a storage means while eliminating the oldest previously stored data bit;

periodically outputting stored data bits in accordance with address command control signals;

supplying reference phase signals;

comparing the phase of output data bits with the phase of the reference phase signals; and

generating address command control signals in accordance with the results of the comparison.

3. Apparatus for delaying a digital data bit stream comprising, in combination:

means for storing incoming data bits in a storage means while eliminating the oldest previously stored data bit;

means for periodically outputting stored data bits from said means for storing incoming data bits in accordance with address command control signals;

means for supplying reference phase signals;

means for comparing the phase of output data bits from said means for periodically outputting stored data bits with the phase of the reference phase signals from said last named means; and

means for generating address command control signals in accordance with the results of the comparison and applying same to said second named means.

4. The method of matching the system delay of a system #1 with the system delay of a system #2 wherein system #1 comprises at least an elastic buffer with an addressable storage for outputting stored data bits upon command comprising the steps of:

applying a data bit stream to both of systems #1 and #2;

detecting the time of occurrence of a periodically occurring signal condition at the output of system #1 and providing a first signal indicative thereof;

detecting the time of occurrence of a periodically occurring signal condition at the output of system #2 and providing a second signal indicative thereof;

comparing the time of occurrence of said first and said second signals with a phase lock loop; and

addressing the addressable storage in the elastic buffer in accordance with the relative time of occurrence of said first and said second signals to maintain equal system delays.

5. Apparatus for matching the system delay of a system #1 with the system delay of a system #2 wherein system #1 comprises at least an elastic buffer with an addressable storage for outputting stored data bits upon command comprising, in combination:

first system means comprising at least an elastic buffer including data input means, data output means and address input means for temporarily storing input data and outputting the data as addressed at a subsequent time as determined by address input signals;

second system means for passing data bits of a data bit stream therethrough and having a time delay in passage which may vary;

means for supplying a stream of data bits to said data input means of both said first and said second system means;

first detection means connected to said data output means of said first system means for detecting the time of occurrence of a periodically occurring signal condition and providing a first signal indicative thereof;

second detection means connected to said data output means of said second system means for detecting the time of occurrence of a periodically occurring signal condition and providing a second signal indicative thereof;

comparison means, comprising at least a phase lock loop means, connected to said first and said second detection means for receiving said first and said second signals therefrom and for comparing the time of occurrence of said first and said second signals; and

address means connected between said comparison means and said address input means of said first system means for providing output address signals to the addressable storage in the elastic buffer of said first system means in accordance with the frequency of operation of a VCO in the phase lock loop.