Circuit arrangement for generating tuning voltage

• US 4,197,503 A
• Filed: 03/03/1978
• Issued: 04/08/1980
• Est. Priority Date: 03/03/1977
• Status: Expired due to Term

• Current Assignee: Skepsy SA
• Original Assignee: Indesit Industria Elettrodomestici Italiana SPA
• Inventors: Dini, Roberto
• Primary Examiner(s): Bookbinder, Marc E.
• Application Number:
  US05/883,236
• Time in Patent Office: 767 Days
• Field of Search: 325/452, 325/453, 325/458, 325/459, 325/464, 325/468, 325/470, 334/15, 331/179, 331/177 V
• US Class Current: 455/195.1
• CPC Class Codes: H03J 3/185 with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03J 5/0263 the digital values being held in an auxiliary non erasable memory

Abstract

The invention relates to broadcast receivers having a voltage controlled tuning device and in particular to a circuit arrangement for applying a voltage to the tuning device. The circuit arrangement is so designed as to be capable of producing tuning voltages to tune the receiver into the desired channels but at the same time being inhibited from producing voltages which tune the receiver into undesired channels such as police channels.

Claims

1. A circuit arrangement for use in controlling a voltage controlled tuning device of a broadcast receiver, said circuit arrangement being adapted to apply a tuning voltage to the tuning device wherein, when the tuning voltage is varied continuously from a lower to an upper limit, the frequency of the tuning device varies continuously over a tuning range which includes all channels from a first lower frequency channel of a first wavelength up to a second higher frequency channel of a second higher wavelength and including an intermediate range of undesired channels whose wavelengths are located between said first lower and said second upper wavelength and in order to prevent reception of said undesired channels, said circuit arrangement including:

first means for producing all tuning voltages between said upper and lower limits including those tuning voltages corresponding to said undesired channels whose frequencies lie in said intermediate range;

analyzing circuit means responsive to said first means for generating a control signal when the tuning voltage developed by said first means reaches at least a predetermined value; and

third circuit means responsive to said control signal for altering the tuning voltage appearing at the output of said first means by a predetermined amount to thereby abruptly skip the tuning voltages representing said undesired channels.

2. A circuit arrangement for applying a tuning voltage to a tuning device of a broadcast receiver, which comprises:

first means for producing a variable voltage wherein, when the tuning voltage is varied continuously from a lower to an upper limit, the frequency of the tuning device varies continuously over a tuning range which includes all channels from a first lower frequency channel of a first wavelength and a second higher frequency channel of a second wavelength and including an intermediate range of undesired channels whose wavelengths lie between said first and second wavelengths;

an analyzing circuit for detecting when the voltage at the output of said first means attains at least a predetermined value; and

an alteration circuit responsive to said analyzing circuit for altering the output voltage developed by said first means by a predetermined amount so that the circuit arrangement is precluded from producing voltages representing said undesired channels.

3. A circuit arrangement claimed in claim 2 further comprising a stabilized voltage source;

a reference voltage source;

a potentiometer connected to said stabilized voltage source and including a wiper arm for developing a variable voltage of a value determined by the position of said wiper arm; and

a voltage comparator for comparing the variable voltage developed by said potentiometer wiper arm with said reference voltage source to produce a control signal which is employed to control the operation of said alteration circuit.

4. A circuit arrangement claimed in claim 3, wherein said alteration circuit includes a switch responsive to said voltage comparator for coupling a portion of said stabilized voltage to the variable voltage appearing at said wiper arm.

5. The circuit arrangement claimed in claim 4, wherein said reference voltage means comprises a voltage divider coupled to said stabilized voltage source for developing said reference voltage.

6. The circuit arrangement of claim 3, wherein said voltage comparator comprises first transistor means having emitter, base and collector electrodes;

said reference voltage source and said variable voltage each being connected to one of said emitter and base electrodes.

7. The circuit arrangement of claim 4, wherein said switch means comprises second transistor means having emitter, base and collector electrodes;

the output of said voltage comparator being connected to the base electrode of said second transistor means.

8. The circuit arrangement of claim 2, wherein said first means further comprises a source of clock pulses;

counter means coupled to said source of clock pulses;

digital to analog converter means being coupled to the output of said counter means for developing an analog voltage representative of the count in said counter means;

decoder means responsive to the count in said counter means and including means for altering the count in said counter means by a predetermined amount when the count in said counter means reaches a first predetermined value for abruptly resetting said counter means to a second predetermined count, thereby causing the output of the digital to analog converter to be abruptly altered.

9. The circuit arrangement of claim 8, wherein said counter means includes preset input means and means for applying a signal corresponding to said second predetermined count to said preset input means;

said counter means being abruptly set to said second predetermined count responsive to the output signal developed by said decoder means.

10. The circuit arrangement of claim 7, wherein the collectors of said first and second transistors are respectively connected to the bases of said second and first transistors, the polarity of the output connections being adapted to provide positive feedback in order to improve the operating speed of the circuit arrangement.

11. The circuit arrangement of claim 7 further comprising first and second resistor means for respectively coupling the output terminal of said circuit arrangement to the collector of said second transistor means and to said wiper arm.

12. The circuit arrangement of claim 11 comprising third transistor means coupled to the common terminal between said wiper arm and said second transistor means and one input of said comparator.