Semiconductor integrated circuit device in which difficulties caused by parasitic transistors are eliminated

• US 4,209,713 A
• Filed: 05/31/1978
• Issued: 06/24/1980
• Est. Priority Date: 07/18/1975
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Electric Co., Ltd.
• Original Assignee: Tokyo Shibaura Electric Co., Ltd.
• Inventors: Satou, Kazuo, Suzuki, Yasoji, Ueno, Mitsuhiko
• Primary Examiner(s): Anagnos, Larry N.
• Application Number:
  US05/911,164
• Time in Patent Office: 755 Days
• Field of Search: 307/200 B, 307/213, 307/214, 307/251, 307/304, 307/205, 330/207 P, 357/42
• US Class Current: 327/310
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit

Abstract

A semiconductor integrated circuit device comprising a CMOS circuit in which parasitic transistors form a parasitic thyristor circuit. In this device, noise absorption resistances are provided at the noise inputs to absorb noise which otherwise might become trigger pulses for the thyristors.

Claims

1. A semiconductor integrated circuit device comprising:

a CMOS circuit having an input part and an output part, the structure of the CMOS circuit characterized by the formation therein of parasitic thyristors;

noise absorption means for absorbing impulse noise that otherwise could become trigger pulses for the thyristors; and

means for connecting said noise absorption means between a source electrode of the CMOS circuit and the positive terminal of an external power source;

said input part of the CMOS circuit being that of a semiconductor integrated circuit device.

2. A semiconductor integrated circuit device comprising:

a CMOS circuit having an input part and an output part, the structure of the CMOS circuit characterized by the formation therein of parasitic thyristors;

noise absorption means for absorbing impulse noise that otherwise could become trigger pulses for the thyristors; and

means for connecting said noise absorption means between a source electrode of the CMOS circuit and the positive terminal of an external power source,

said output part of the CMOS circuit being that of a semiconductor integrated circuit device.

3. A semiconductor integrated circuit device comprising:

a CMOS circuit having an input part and an output part, the structure of the CMOS circuit characterized by the formation therein of parasitic thyristors;

noise absorption means for absorbing impulse noise that otherwise could become trigger pulses for the thyristors; and

means for connecting said noise absorption means between a source electrode of the CMOS circuit and the negative terminal of an external power source,

said input part of the CMOS circuit being that of a semiconductor integrated circuit device.

4. A semiconductor integrated circuit device comprising:

a CMOS circuit having an input part and an output part, the structure of the CMOS circuit characterized by the formation therein of parasitic thyristors;

noise absorption means for absorbing impulse noise that otherwise could become trigger pulses for the thyristors; and

means for connecting said noise absorption means between a source electrode of the CMOS circuit and the negative terminal of an external power source,

said output part of the CMOS circuit being that of a semiconductor integrated circuit device.