Sensing amplifier for floating gate memory devices

• US 4,223,394 A
• Filed: 02/13/1979
• Issued: 09/16/1980
• Est. Priority Date: 02/13/1979
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Pathak, Saroj, Perlegos, George
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/011,915
• Time in Patent Office: 581 Days
• Field of Search: 307/238,279, 365/189, 365/190, 365/104, 365/202, 365/203, 365/207, 365/210, 365/230, 365/185
• US Class Current: 365/185.21
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

An MOS sensing amplifier for sensing the binary state of floating gate memory devices in a read-only memory is disclosed. The potentials on the column lines in the memory are held to a narrow voltage swing. A pair of "zero" threshold voltage transistors having slightly different threshold voltages are used to maintain the potentials on these lines. A potential developed from the column line is compared with a reference potential developed with a "dummy" biasing network and a "dummy" floating gate memory device.

Claims

1. An amplifier for sensing the binary state of a first MOS floating gate memory device comprising:

a line coupled to said first device;

a first biasing means coupled to said line for charging said line to a first potential when said first device is in one binary state and for preventing said line from dropping below a second potential when said first device is in its other binary state;

a second floating gate memory device substantially identical to said first device for providing a reference load;

a biasing circuit coupled to said second device for biasing said second device at a predetermined level;

a second biasing means coupled to said second device for providing a reference potential;

comparator means for comparing potentials, said comparator means coupled to said line and coupled to receive said reference potential;

whereby said amplifier senses said binary state of said first device and is quickly able to again sense the binary state of said first device since said line is prevented from discharging by said first biasing means.

2. The amplifier defined by claim 1 wherein said first and second biasing means are substantially identical circuits.

3. The amplifier defined by claim 1 wherein said first biasing means includes a first and a second transistor coupled to said line, said transistors having a difference in threshold voltages equal to the difference between said first and second potentials.

4. The amplifier defined by claim 3 wherein said first and second transistors are devices having threshold voltages close to zero volts.

5. The amplifier defined by claim 4 wherein said second biasing means is substantially identical to said first biasing means.

6. The amplifier defined by claim 5 wherein said comparator means is a differential amplifier.

7. In a read-only memory which includes a plurality of floating gate memory devices which are selectively coupled to a line in said memory, a sensing amplifier coupled to said line for detecting the binary state of said memory devices comprising:

a first biasing means coupled to said line for charging said line to a first potential when a selected one of said memory devices is in one binary state and for preventing said line from dropping below a second potential when said selected one of said memory devices is in its other binary state;

an additional floating gate device substantially identical to said memory devices for providing a reference load;

a biasing circuit coupled to the control gate of said additional device for biasing said additional device such that said additional device conducts;

a second biasing means substantially identical to said first biasing means for providing a reference potential, said second biasing means coupled to said additional device;

comparator means for comparing two potentials, said comparator means coupled to said line and coupled to receive said reference potential;

whereby said amplifier quickly senses said binary states of said devices since said line is prevented from discharging.

8. The amplifier defined by claim 7 wherein said first biasing means comprises:

a first transistor coupled to a source of potential;

a second transistor coupled between said first transistor and said line;

a third transistor coupled between said source of potential and said line.

9. The amplifier defined by claim 8 wherein said second and third transistors have different threshold voltages.

10. The amplifier defined by claim 9 wherein the differences in said threshold voltages of said second and third transistors is equal to the difference between said first and second potentials.

11. The amplfier defined by claim 10 wherein the gates of said second and third transistors are coupled to a common biasing means.

12. The amplifier defined by claim 11 wherein said second and third transistors have threshold voltages close to zero volts.

13. The amplifier defined by claim 12 wherein said difference in said threshold voltages is in the order of magnitude of 0.1 volts.

14. The amplifier defined by claim 13 wherein said comparator means is a differential amplifier.

15. The amplifier defined by claim 13 wherein said second biasing means is coupled to said additional device through a fourth transistor, said fourth transistor being identical to transistors employed in said memory for said selective coupling of said memory devices to said line.