Intersystem transaction identification logic
First Claim
1. In a data processing network including a plurality of data processing systems wherein each system is provided with common bus means for exchanging information between individual devices within said system, intersystem communication control apparatus comprising:
- first logic control means coupled to a first one of said common bus means responsive to memory and non-memory access commands presented on said first common bus means for generating an address signal identifying a remote target device which is to be accessed in response to an access command;
programmable memory means operable in response to said address signal to indicate whether said remote target device to be accessed can be accessed through the control apparatus, said programmable memory means having stored in predetermined memory locations thereof first and second binary bit signals indicative of remote memory and non-memory target devices coupled to a second one of said common bus means;
second logic control means for applying said address signal to said programmable memory means to read therefrom a binary bit signal indicating that a remote target device is selected by said access command;
register means having dedicated register locations coupled to said first common bus means and including a memory request storage location and a retry request storage location, said register means operating in response to presentation on said first common bus means of a memory access command to load into said memory request storage location data from said first common bus means, said register means further operating in response to presentation of a non-memory access command to load into said retry storage location data from said first common bus means; and
transfer logic means responsive to a first binary bit read from said programmable memory means for transferring the data in said memory request storage location to said second common bus means for accessing a remote memory target device coupled thereto, said transfer logic means further being responsive to a second binary bit read from said programmable memory means for transferring the data in said retry request storage location to said second common bus means for accessing a remote non-memory target device coupled thereto.
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Abstract
A logic system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein dedicated locations in a file register are selected at the bus rate in response to binary coded information received from a local communication bus. ISL transactions to be initiated in response to bus cycle requests thereby are identified. ISL transactions are handled in parallel, and memory transfers are segregated from non-memory transfers to avoid unnecessary delays in memory transfers.
66 Citations
10 Claims
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1. In a data processing network including a plurality of data processing systems wherein each system is provided with common bus means for exchanging information between individual devices within said system, intersystem communication control apparatus comprising:
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first logic control means coupled to a first one of said common bus means responsive to memory and non-memory access commands presented on said first common bus means for generating an address signal identifying a remote target device which is to be accessed in response to an access command; programmable memory means operable in response to said address signal to indicate whether said remote target device to be accessed can be accessed through the control apparatus, said programmable memory means having stored in predetermined memory locations thereof first and second binary bit signals indicative of remote memory and non-memory target devices coupled to a second one of said common bus means; second logic control means for applying said address signal to said programmable memory means to read therefrom a binary bit signal indicating that a remote target device is selected by said access command; register means having dedicated register locations coupled to said first common bus means and including a memory request storage location and a retry request storage location, said register means operating in response to presentation on said first common bus means of a memory access command to load into said memory request storage location data from said first common bus means, said register means further operating in response to presentation of a non-memory access command to load into said retry storage location data from said first common bus means; and transfer logic means responsive to a first binary bit read from said programmable memory means for transferring the data in said memory request storage location to said second common bus means for accessing a remote memory target device coupled thereto, said transfer logic means further being responsive to a second binary bit read from said programmable memory means for transferring the data in said retry request storage location to said second common bus means for accessing a remote non-memory target device coupled thereto. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification