Substrate bias generator

• US 4,255,756 A
• Filed: 01/03/1980
• Issued: 03/10/1981
• Est. Priority Date: 01/05/1979
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Shimotori, Kazuhiro, Nakano, Takao, Nagayama, Yasuzi
• Primary Examiner(s): Edlow, Martin H.
• Application Number:
  US06/109,399
• Time in Patent Office: 432 Days
• Field of Search: 357/41, 357/51, 357/23, 307/304
• US Class Current: 257/299
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: H01L 27/0222 Charge pumping, substrate bias generation structures
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout

Abstract

The disposed substrate bias generator comprises a capacitor including an electrically insulating film sandwiched between two electrodes one of which is disposed on one main face of a p^- semiconductor substrate through another electrically insulating film, and a first, a second and a third N⁺ semiconductor region disposed in spaced relationship on the same main face. The first and second regions form a grounded source and a drain of an MOSFET connected to both its gate and one of the electrodes of the capacitor. The second and third regions form a source and a drain of another MOSFET connected to both its gate and the other main face of the substrate. A signal is applied to the other electrode of the capacitor.

Claims

1. A substrate bias generator for generating a potential in a semiconductor substrate, comprising a semiconductor substrate of a first type conductivity including a pair of first and second main faces opposite to each other, a first, a second and a third semiconductor regions of a second type conductivity disposed at predetermined intervals on said first main face of said semiconductor substrate, a first MOSFET disposed on said first main face of said semiconductor substrate and including a source region formed of said first semiconductor region, a drain region formed of said second semiconductor region and a gate electrode, a second MOSFET disposed on said first main face of said semiconductor substrate and including a source region formed of said second semiconductor region, a drain region formed of said third semiconductor region, and a gate electrode, a capacitor disposed on said first main face of said semiconductor substrate through an electrically insulating film, said capacitor including a pair of opposite electrodes and another electrically insulating film interposed between said electrodes, a first electric lead for connecting one of said electrodes of said capacitor to said gate electrode and drain region of said first MOSFET, and a second electric lead for connecting said gate electrode and drain region of said second MOSFET to an electrode connected to said second main face of said semiconductor substrate, said capacitor having a signal applied to the other electrode thereof, said first MOSFET having a source electrode connected to a ground potential.

2. A substrate bias generator as claimed in claim 1 wherein said capacitor includes one electrode disposed on said first main face of said semiconductor substrate through said electrically insulating film and connected to said gate electrode and drain region of said first MOSFET through said first electric lead, and the other electrode disposed on said one electrode through said another electrically insulating film and applied with said signal.

3. A substrate bias generator as claimed in claim 1 wherein said capacitor includes one electrode disposed on said first main face of said semiconductor substrate through said electrically insulating film and having said signal applied thereto and the other electrode disposed on said one electrode through said another electrically insulating film and connected to said gate electrode and drain region of said first MOSFET through said first electric lead.

4. A substrate bias generator as claimed in claim 1 wherein said semiconductor substrate has a P type conductivity and each of said first, second and third semiconductor zones has an N type conductivity.

5. A substrate bias generator as claimed in claim 1 wherein said semiconductor substrate has an N type conductivity and each of said first, second and third semiconductor regions has a P type conductivity.