Low voltage CMOS amplifier
First Claim
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1. A CMOS amplifier comprising:
- a first pair of CMOS devices having their source-drain conduction paths connected in series between voltage supply terminals, one of said CMOS devices being a load MOS and the other being an amplifier MOS;
means connected to the gate of said load MOS and said voltage supply terminals for biasing said load MOS independent of voltage supply variations to produce a constant current source to said amplifier MOS;
means interconnecting the drain of said amplifying MOS and the gate of said amplifying MOS for providing a nonlinear negative feedback; and
a first resistance connected in parallel with said feedback means and a second resistance connected between the output of said MOS amplifier and the drain junction of said load and amplifying MOS devices.
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Abstract
A CMOS amplifier having a pair of CMOS load and amplifying devices connected in series, two parallel pairs of CMOS devices with interconnected gates to form current mirrors and connected to the gate of the load MOS device to compensate the gain for variations in power supply voltage, temperature and transistor parameters, a feedback MOS device having its source-drain path connected between the junction of the load and amplifying MOS and the gate of the amplifying MOS to provide nonlinear, negative feedback, and a resistor connected in parallel with the feedback MOS device to establish an initial self-biasing voltage level for the amplifying MOS below the threshold voltage of the feedback MOS.
67 Citations
21 Claims
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1. A CMOS amplifier comprising:
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a first pair of CMOS devices having their source-drain conduction paths connected in series between voltage supply terminals, one of said CMOS devices being a load MOS and the other being an amplifier MOS; means connected to the gate of said load MOS and said voltage supply terminals for biasing said load MOS independent of voltage supply variations to produce a constant current source to said amplifier MOS; means interconnecting the drain of said amplifying MOS and the gate of said amplifying MOS for providing a nonlinear negative feedback; and a first resistance connected in parallel with said feedback means and a second resistance connected between the output of said MOS amplifier and the drain junction of said load and amplifying MOS devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A CMOS amplifier comprising:
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a pair of CMOS devices having their source-drain conduction paths connected in series, one of said CMOS devices being a load device and the other an amplifying device; first MOS means connected to said load device for varying said load to maintain the gain of said amplifier constant independent of variations in the power supply voltage; second MOS means for producing a non-linear negative feedback from the output of said amplifying device to its input to thereby establish a stable self-biasing voltage level for said amplifying device; and a first resistance means connected between said amplifying device and the output of said MOS amplifier for minimizing the variations of output impedence and a second resistive means connected in parallel with said non-linear negative feedback MOS means for establishing an initial self-biasing voltage level below the threshold level of said second MOS means. - View Dependent Claims (10)
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11. In an oscillator having an inverting amplifier whose input and output are connected to a frequency determine network, the improvement in said inverting amplifier comprising:
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a load MOS device and a complementary amplifying MOS device having their source-drain conduction paths connected in series; two pairs of CMOS devices, each pair connected in parallel to said series connected load and amplifying devices, the gates of common channel type devices of said CMOS pairs being interconnected and connected to opposite CMOS pair junctions; the gate of said load MOS device being connected to the drain junction of one of said pairs to which the gates of said MOS devices of the same channel type as said load devices are connected; and a feedback MOS device having its source-drain conduction path connected between the junction of the load and amplifying MOS devices and the gate of said amplifying MOS device. - View Dependent Claims (12, 13, 14, 15)
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17. In combination with a power supply, a CMOS amplifier comprising a first pair of CMOS devices, one of said devices operating as an amplifier device, the other as a load device to said amplifier device, the improvement comprising:
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bias means connected to said load device for varying the bias to the gate of said load device in response to variations in said power supply, said bias means including a current mirror circuit and a current responsive circuit means connected to said current mirror and said load device for controlling the bias to said load device in response to current variations in said current mirror circuit; and non-linear feedback means connected to said amplifier device for establishing the self-biasing voltage level for the amplifier device. - View Dependent Claims (16, 18, 19, 20, 21)
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Specification