HVMOSFET Driver with single-poly gate structure

• US 4,288,802 A
• Filed: 08/17/1979
• Issued: 09/08/1981
• Est. Priority Date: 08/17/1979
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Ronen, Ram S.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US06/043,870
• Time in Patent Office: 753 Days
• Field of Search: 357/23, 357/24, 357/41, 357/45, 357/52, 357/55, 357/56, 357/50, 357/51, 357/53, 357/68, 357/91
• US Class Current: 257/409
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/405 Resistive arrangements, e.g. resistive or semi-insulating field plates
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

Integrated monolithic arrays of high voltage metal oxide semiconductor field effect transistors having closed geometry grounded peripheries for inter-device isolation are able to function as drivers that may be switched on and off. The HVMOSFET'"'"'S includes DMOS-like structures with separate channel and drift regions, closed geometry configurations with center drains, and split oxide topography having relatively thin oxide under a control gate and over a channel region, and relatively thick oxide under a field plate and over a drift region for surface depletion and high voltage field inversion preclusion respectfully. The infra described HVMOSFET with single polysilicon layers for non-overlapping gates is operative to bend field lines away from the drain oven thereby increasing the available breakdown voltage adjacent to the drain area.

Claims

1. A MOSFET component for use as a monolithic integrated array on a substrate having closed geometry including a drain area as a relative center axis introduced in the substrate, a source area introduced in the substrate relatively concentric and adjacent to the drain area, a channel area introduced in the substrate between the source area and drain areas which it is relatively concentric to, and a drift area introduced in the substrate between the channel area and drain area which it is relatively concentric to, comprising:

(a) first gate means embedded in a first layer of relatively thick oxide relatively disposed over the drift area for applying a relatively high voltage potential through the first layer to the drift area for stretching out the field lines away from the drain area; and

,

(b) second gate means embedded in a second layer of relatively relative thin oxide relatively disposed over the channel area and introduced as part of the same relatively non-overlapping layer as said first gate means for controlling the potential and for turning on and off the current between the source and drain areas.

2. The MOSFET component of claim 1 wherein said first gate means is polysilicon.

3. The MOSFET component of claim 1 wherein said first gate means may be relatively discretely partitioned with relatively decreasing non-equal potentials applied to each thereof relative to the drain area.

4. The MOSFET component of claim 1 wherein said second gate means is polysilicon.

5. The MOSFET component of claim 1 wherein said second gate means may have a relatively low potential applied thereto.

6. The MOSFET component of claim 1 wherein said first gate means has relatively disposed above and in proximate spatial contact has therewith a third layer of oxide for inter-device solution.

7. The MOSFET component of claim 1 wherein said second gate means has relatively disposed above and in proximate spatial contact therewith a fourth layer of oxide for inter-device isolation.

8. The MOSFET component of claim 1 wherein there is a gap between said first and second gate means of relatively minimal spacing for accommodating substrate field lines without avalanche setting in and for preventing oxide breakdown.

9. The MOSFET component of claim 1 wherein said first layer of relatively thick oxide having said second gate means embedded therein lies in a relative indentation in the substrate.

10. A high voltage MOSFET apparatus for use in a monolithic integrated array on a substrate as a driver, comprising:

(a) first means having a relative center axis implanted in the substrate for operation as a drain area, second means implanted in the substrate relatively adjacent and concentric to said first means for operation as a source area, third means is the substrate between said second means and first means which it is relatively concentric to for operation as a channel area, and fourth means implanted in the substrate between said third means and first means which it is relatively concentric to for operation as a drift area.

(b) first gate means embedded in a first layer of relatively thin oxide relatively disposed over said third means for controlling the potential and for turning on and off the current between said first and second means; and

(c) second gate means embedded in a second layer of relatively thick oxide relatively disposed over said fourth means for stretching out field lines from said first means and for increasing the breakdown voltage in said second layer of relatively thick oxide.

11. The high voltage MOSFET apparatus of claim 10 wherein said first gate means is polysilicon.

12. The high voltage MOSFET apparatus of claim 10 wherein said first gate means may be discretely partitioned with relatively descending non-equal potentials applied to each thereof relative to the said first means.

13. The high voltage MOSFET apparatus of claim 10 wherein said second gate means is polysilicon.

14. The high voltage MOSFET apparatus of claim 10 wherein said second gate means may have a relatively low potential applied thereto.

15. The high voltage MOSFET apparatus of claim 10 wherein said first gate means has a relatively disposed above and in proximate spatial contact therewith a third layer of oxide for inter-device isolation.

16. The high voltage MOSFET apparatus of claim 10 wherein said second gate means has relatively disposed above and in proximate spatial contact therein a fourth layer of oxide for inter-device isolation.

17. The high voltage MOSFET apparatus of claim 10 wherein there is a relative gap between said first and second gate means of relatively minimal spacing for accommodating substrate field lines without avalanche setting in and for precluding oxide breakdown.

18. The high voltage MOSFET apparatus of claim 10 wherein said first layer of relatively thick oxide having said second gate means embedded therein lies in a relative indentation in the substrate.