Memory circuit

• US 4,288,862 A
• Filed: 12/19/1978
• Issued: 09/08/1981
• Est. Priority Date: 12/21/1977
• Status: Expired due to Term

• Current Assignee: Nippon Telegraph and Telephone Corporation
• Original Assignee: Hitachi, Ltd., Nippon Telegraph and Telephone East Corporation (Nippon Telegraph and Telephone Corporation)
• Inventors: Suzuki, Hideo, Ohhinata, Ichiro, Ohkoshi, Seiei
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US05/971,109
• Time in Patent Office: 994 Days
• Field of Search: 307/238, 307/252 A, 307/252 C, 307/252 G, 307/284, 307/288, 307/305, 307/313, 365/154, 365/155, 365/156, 365/180, 365/181
• US Class Current: 365/181
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 11/411 using bipolar transistors only
• CPC Class Codes: H03K 3/352 the devices being thyristors

Abstract

A memory circuit comprising a memory cell for storing information, constituted of semiconductor circuit elements and the associated circuit elements, and a control input section provided on the input side of the memory cell for controlling the memory cell, constituted of transistor means and current control means, wherein one of ON and OFF states is selected and also held in accordance with more than two logic input signals supplied to the control input section and no power is consumed to hold the OFF state.

Claims

1. A memory circuit comprising

a memory cell including two complementary transistors operatively connected to form a four-layer semiconductor having an input for receiving a data signal to be stored therein,

a control input circuit including transistor means having at least one input transistor with its collector connected to the input of said memory cell,

first input means connected to said control input circuit including first, econd and third input terminals receiving respective logical signals,

second input means including a fourth input terminal receiving a data signal to be stored in said memory cell, means for connecting said fourth input terminal to an emitter of said input transistor and

said control input circuit further including control means for controlling the base current of said input transistor on the basis of a logical product of the signals applied to said first, second and third input terminals.

2. A memory circuit as claimed in claim 1, wherein said control means is constituted of at least first and second diodes, and said input transistor has its base connected through an impedance element with said first input terminal, and said first and second diodes having their anodes connected in common with said base of said input transistor and their cathodes connected to said second and third input terminals, respectively.

3. A memory circuit as claimed in claim 2, wherein the emitter-base junctions of PNP transistors with their collectors connected in common and grounded are used as said first and second diodes with their cathodes connected to said second and third input terminals.

4. A memory circuit as claimed in claim 1, wherein said transistor means is constituted of at least said input transistor and an additional transistor and said control means is constituted of at least one diode, said input transistor having its base connected with one of the emitter and the collector of said additional transistor, said additional transistor having its base connected through an impedance element with said first input terminal and its emitter or collector, which is not connected with said base of said input transistor, connected with said third input terminal, said one diode having its cathode connected to said second input terminal and its anode connected to said base of said input transistor.

5. A memory circuit as claimed in claim 4, wherein the emitter-base junctions of PNP transistors with their collectors connected in common and grounded are used as said first and second diodes with their cathodes first input terminal and the fourth and further input terminals.

7. A memory circuit as claimed in claim 1, wherein said transistor means comprises at least said input transistor and an additional transistor and said control means comprises at least first and second diodes, said input transistor having its base connected with one of the emitter and the collector of said additional transistor and its emitter connected to said fourth input terminal through third and fourth diodes connected in inverse parallel configuration with each other, said additional transistor having its base connected to said second input terminal through an impedance element and its emitter or collector, which is not connected with said base of said input transistor, connected with said third input terminal, and said first and second diodes having their cathodes connected to said first input terminal and a further input terminal, respectively, and their anodes connected in common to said base of said input transistor.

8. A memory circuit as claimed in claim 7, wherein the emitter-base junctions of PNP transistors with their collectors connected in common and grounded are used as said first through fourth diodes with their cathodes used as said first input teminal and further input terminal.

9. A memory cicuit as claimed in claim 4 or claim 7, wherein said additional transistor is an NPN transistor with its emitter connected with said base of said input transistor.

10. A memory circuit as claimed in claim 4 or claim 7, wherein said additional transistor is a PNP transistor with its collector connected with said base of said input transistor.

11. A memory circuit as claimed in claim 1, wherein said control means comprises at least first and second diodes, and said input transistor has its base connected through a series circuit of two impedance elements to the first input terminal and its emitter connected a further diode to said fourth input terminal of said memory circuit, and said first and second diodes have their cathode connected to said second and third input terminals and their anodes connected in common with the junction point of said impedance elements.

6. A memory circuit as claimed in claim 12, wherein said control means is constituted of at least first and second diodes, and said input transistor has its base connected through an impedance element with said first input terminal and its emitter connected through third and fourth diodes connected in inverse parallel configuration with each other to said fourth input terminal, said first and second diodes having their cathodes connected respectively to said second and third input terminals and their anodes connected in common with said base of said input transistor.