Digital readout PRF measuring device

• US 4,303,921 A
• Filed: 01/02/1970
• Issued: 12/01/1981
• Est. Priority Date: 01/02/1970
• Status: Expired due to Term

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Olsen, Robert C., Fitzgerald, David L.
• Primary Examiner(s): Tubbesing, T. H.
• Application Number:
  US05/005,389
• Time in Patent Office: 4,351 Days
• Field of Search: 343/17.7, 343/18 E
• US Class Current: 342/13
• CPC Class Codes: G01S 7/021 Auxiliary means for detecting or identifying radar signals or the like, e.g. radar jamming signals

Abstract

A pulse repetition frequency (PRF) expanded display and coincident gating ectronic intelligence gathering circuit for incorporating in radar receivers having the capability of gating the PRF signals of unknown origin to sort out signals having a particular PRF or band of PRFs with accuracy and resolution in a digital readout, with switching modes and switching positions to present several modes of intelligence about the PRF emitter.

Claims

1. An electronic intelligence signal processing circuit for coupling into the video circuit of a radar receiver for displaying and digitally reading out the PRF count of known and unknown PRF emitters comprising:

an input of raw video PRF signals;

an adjustable threshold detector coupled to said input to detect frequency signals above the adjusted threshold and for standardizing each detected frequency signal, said detector having an output;

a phase lock loop coupled to the output of said threshold detector with an adjustable comparator therein to adjust the leading edge of a pulse, the trailing edge of which is positioned by a PRF signal, said phase lock loop having an output;

synchronous, marker, and delay one-shot multivibrator circuits coupled in common to the output of said phase lock loop, said marker and delay one-shots having width and delay controls therein, respectively, each one-shot having outputs;

a summing amplifier having a plurality of inputs and a system output, said synchronous and marker one-shot outputs being coupled to inputs thereof, and said raw video input and standardized video being coupled to inputs thereof;

a gate one-shot, a marker gate inverter, and a linear gate being intercoupled, said gate one-shot being coupled to the output of said delay one-shot, and said marker gate inverter and said linear gate being coupled to the output of said marker one-shot with one output of said linear gate being coupled to said summing amplifier, said marker gate inverter having a system output for producing marker pulses thereon and said linear gate having a system output for producing gated video signals thereon, said linear gate system output being coupled in parallel with an audio amplifier for producing an audio output thereon;

a counter and digital readout circuit means having inputs coupled to said audio amplifier output, to said delay one-shot output, and to said raw video input to count PRF signals and simulated signals for digital readout to provide a numerical count of the signals produced on said system outputs; and

selector switch means in said couplings for switching the circuit in various combinations of elements to different modes and switched positions to provide different types of information and test of known and unknown emitted PRF signals.

2. An electronic intelligence signal processing circuit as set forth in claim 1 wherein

said phase lock loop includes a phase gate, a reset one-shot, a reset switch, a sawtooth generator, and a comparator with a variable reference voltage as a second input constituting said adjustable comparator, in this order from input to output, the output of said comparator being looped back as a second input to said phase gate together with an output of said delay one-shot to produce a phase lockon to standardized PRF video signals applied to the input thereof.

3. An electronic intelligence signal processing circuit as set forth in claim 1 wherein

said synchronous one-shot produces a single negative fixed width output pulse, said marker and delay one-shots each have positive and negative outputs said marker one-shot having a manual width control to time the duration of output pulses and said delay one-shot having a manual delay control to delay the time of the output pulses, said output pulses from said delay one-shot to said phase gate and to said gate one-shot being through rise time restorer circuits.

4. An electronic intelligence signal processing circuit as set forth in claim 3 wherein

said counter and digital readout circuit means includes an oscillator operating through a time base count down circuit to a counter gate which gates all inputs to a digital counter for numeric display, said time base count down circuit having its output coupled also to a reset gate operating through a reset one-shot and a reset switch to reset said digital counter, and wherein said coupling from said audio amplifier to said counter and digital readout circuit means is through an amplifier inverter, a peak detector, and shaper inverter to said counter gate.

5. An electronic intelligence signal processing circuit as set forth in claim 4 wherein

said system outputs from said marker gate inverter, said linear gate, and said summing amplifier are through emitter followers to provide low impedance isolation output couplings adapted to be coupled to a radar analyzer display.

6. An electronic intelligence signal processing circuit as set forth in claim 5 wherein

said selector switch means consists of one selector switch capable of circuiting combinations of the above-claimed elements for Bypass, Marker, Expand, Selector and Generate Modes of operation and of another selector switch capable of circuiting combinations of the above-claimed elements for PRF, Scan, Seconds Per Revolution, Test and External Positions of operation to provide different types of output information.

7. An electronic intelligence signal processing circuit as set forth in claim 6 wherein

said phase lock loop includes a chopper circuit switchable by said selector switch in the expand mode to chop the inputs to said reset one-shot to time share more than one PRF signal applied to said input.

8. An electronic intelligence signal processing circuit as set forth in claim 7 wherein

said external position of said other selector switch connects an external PRF simulated signal source to said summing amplifier to produce a simulated video output.