Digital computer having code conversion apparatus for an encrypted program

• US 4,306,289 A
• Filed: 02/04/1980
• Issued: 12/15/1981
• Est. Priority Date: 02/04/1980
• Status: Expired due to Term

• Current Assignee: AT&T, Inc.
• Original Assignee: Western Electric Co., Inc. (Nokia Corporation)
• Inventors: Lumley, Robert M.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US06/118,003
• Time in Patent Office: 680 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 375/2, 178/22
• US Class Current: 713/190
• CPC Class Codes: G06F 21/101 by binding digital rights to specific entities
• CPC Class Codes: G06F 21/123 by using dedicated hardware, e.g. dongles, smart cards, cryptographic processors, global positioning systems [GPS] devices
• CPC Class Codes: G06F 21/72 in cryptographic circuits

Abstract

The architecture of a conventional digital computer, for example, a microprocessor, is modified by interposing a multiplexer (31), a logic array (32) and a demultiplexer (33) between the instruction register (17) and instruction decoder (18). The logic array "scrambles" the bits in each instruction code; however, if the program to be run is priorly encrypted with this "scrambling" in mind, it will run normally. On the other hand, if the encrypted program is copied, the copied program will not run on an unmodified computer.

Claims

1. An improved electronic digital computer comprising:

an internal data bus;

a register array coupled to said internal bus and including a plurality of general purpose data registers;

an accumulator connected to said internal data bus;

an arithmetic logic unit connected to said accumulator and to said internal data bus for performing logical operations on the data stored in said accumulator and in said general purpose registers;

an instruction register connected to said internal data and adapted to receive program instruction codes; and

an instruction decoder connected to said instruction register and responsive to selected ones of said program instruction codes, WHEREIN THE IMPROVEMENT COMPRISES

means, within the electronic digital computer, interposed between said instruction register and said instruction decoder, for selectively transforming the bit pattern of a program instruction code into a second instruction code thereby enabling said computer to selectively respond to sequences of program instruction codes which have priorly been encrypted as instruction codes in non-standard format.

2. The computer according to claim 1, wherein said transforming means comprises:

a first multiplexer connected to the output of said instruction register;

a logic array circuit connected to the output of said first multiplexer for producing a predetermined translation between the bits comprising the instruction code input thereto and the instruction code output therefrom;

a second multiplexer connected to the output of said logic array circuit; and

means for activating said first and second multiplexers such that the flow of program instruction code from said instruction register to said instruction decoder selectively bypasses said logic circuit.

3. The computer according to claim 2, wherein said logic array circuit comprises a plurality of logic gates interconnected in accordance with a predetermined pattern and interposed between the input of said logic array circuit and the output thereof for producing a predetermined fixed translation of the bits comprising said program instruction code.

4. The computer according to claim 2, wherein said logic array circuit comprises:

a plurality of logic subarray circuits, each comprising a plurality of logic gates interconnected in accordance with a predetermined pattern, said logic subarray circuits being interposed between the input of said logic array circuit and the output thereof; and

means coupled to the logic subarray circuits for selectively routing the flow of program instruction codes through a particular one of said logic subarray circuits.

5. The computer according to claim 4, further comprising:

means, responsive to a control signal from said instruction decoder, for selectively routing the flow of program instruction codes through different ones of said plurality of logic subarray circuits during execution of a sequence of program instruction codes.

6. The apparatus according to claim 2, wherein said logic array circuit comprises:

a plurality of logical elements each having at least two inputs, one of which connects to the corresponding bit input of said program instruction code; and

a pseudo-random generator having a plurality of outputs each of which connects to a corresponding other input of said logic elements, whereby the bit translation effected between an incoming program instruction code and the output program instruction code changes, in a pseudo-random fashion, at predetermined intervals during the execution of said program.

7. The apparatus according to claim 2, wherein said logic array circuit comprises:

a read-only memory having a plurality of address lines and a corresponding plurality of data output lines, said address lines being connected to said instruction register via said first multiplexer and said data output lines being connected to said instruction decoder via said second multiplexer whereby the selective bit transposition is effected by means of a look-up table priorly stored in said read-only memory.