Self organizing general pattern class separator and identifier

• US 4,326,259 A
• Filed: 03/27/1980
• Issued: 04/20/1982
• Est. Priority Date: 03/27/1980
• Status: Expired due to Term

• Current Assignee: Nestor, Inc.
• Original Assignee: Nestor Associates
• Inventors: Cooper, Leon N., Reilly, Douglas L., Elbaum, Charles
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US06/134,571
• Time in Patent Office: 754 Days
• Field of Search: 364/715, 364/900, 340/146.3 T, 340/146.3 Z
• US Class Current: 708/212
• CPC Class Codes: G06F 18/24143 Distances to neighbourhood prototypes, e.g. restricted Coulomb energy networks [RCEN]

Abstract

A system is provided for the separation into and the indentification of classes of events wherein each of the events is represented by a signal vector comprising the signals s, s_z . . . , s_j . . . , s_N. The system comprises a plurality of assemblies, each of the assemblies including a matrix of junction elements for respectively receiving as inputs the different respective signals of a vector. The junction elements provide a transfer of information A_ij s,; i.e., the product of the transfer function of the element and the signal input applied thereto. The information transferred by the junction elements is summed in each assembly. In the training mode of operation information summed in each assembly is applied to a scalar multiplier and the resulting information is in turn applied to a threshold stage which is actuated to produce an output if the input applied thereto attains a prescribed value. Concurrently, the summed outputs of the junction elements are fed back to these elements to modify their transfer functions. The outputs of the threshold stages are finally processed for identification of the classes of events.

Claims

1. An information processing system for separating classes of non-linearly as well as linearly separable patterns, each of said patterns being represented by a plurality N of input signals s₁, s₂, . . . s_j . . . s_N, said system comprising, in combination:

(a) a plurality N of input terminals, each terminal (j) adapted to receive one of the N input signals (s_j);

(b) a plurality M of summing means, each summing means (i) having N inputs and an output and being operative to provide a signal (p'"'"'_i) at its output representing the sum of the signal representations applied to its inputs;

(c) a plurality N×

M of junction elements, each junction element (ij) coupling one of said input terminals (j) with one summing means (i) and providing a transfer of information from the respective input terminal j to the respective summing means i in dependence upon the signal (s_j) appearing at the input terminal and upon the element transfer function A_ij ;

(d) a plurality M of threshold means, each threshold means (i) coupled to the output of one of said summing means (i) and adapted to produce an output (p_i) whenever the output signal (p'"'"'_i) produced by the respective summing means exceeds a given threshold value (θ

_pi),

whereby the output P represented by the respective output signals p₁, P₂ . . . p_i . . . p_M of said threshold means provide a separation of the patterns represented by said input signals s₁, s₂, . . . s_j . . . s_N into classes.

2. A system as defined in claim 1, further comprising a Nestor adaptive module connected to receive the output signals p₁, p₂, . . . p_i . . . p_M of said threshold means for producing an output R represented by respective output signals r_i, r₂ . . . r_l . . . r_k.

3. A system as defined in claim 1, wherein each of said threshold means include means for modifying the respective output signal p'"'"'_i of said summing means with a respective chosen factor, and means for comparing the modified output with said threshold value and producing said output (p_i) in response thereto.

4. A system as defined in claim 3, wherein each of said signal modifying means is a scalar multiplying means for multiplying said output signal p'"'"'_i by a respective scalar factor λ

_i.

5. A system as defined in claim 4, further comprising means for selectively adjusting said scalar factor λ

_i, when in a training mode, in dependence upon whether an incoming pattern is correctly or incorrectly identified by production of the output p_i of the associated threshold means.

6. A system as defined in claim 5, wherein said scalar factor adjusting means comprises means for reducing the scalar factor λ

_i when an incoming pattern is incorrectly identified with a prototype by the threshold means with which that particular factor λ

_i is associated.

7. A system as defined in claim 6, wherein said scalar factor reducing means decrements said scalar factor by a prescribed amount each time an incoming pattern is incorrectly identified.

8. A system as defined in any one of claims 4-7, further comprising means for setting each scalar factor λ

_i to a maximum value λ

°

_i, thereby to associate committed prototypes with the scalar factors at their maximum values.

9. A system as defined in claim 1, further comprising means for selectively adjusting the threshold value θ

_pi of a threshold means, when in a training mode, in dependence upon whether an incoming pattern is correctly or incorrectly identified by production of the output p_i of that threshold means.

10. A system as defined in claim 9, wherein said threshold value adjusting means comprises means for increasing the threshold value θ

_pi when an incoming pattern is incorrectly identified with a prototype by the threshold means with which that particular threshold value θ

_pi is associated.

11. A system as defined in either one of claims 9 and 10, further comprising means for setting each threshold value θ

_pi to a minimum value θ

°

_pi, thereby to commence training with minimum threshold values.

12. A system as defined in any one of claims 1-10, wherein said threshold means is a trigger circuit which is actuated in response to an input thereto of at least said given threshold value.

13. A system as defined in any one of claims 1-10, further comprising class identifying means responsive to the output signals p₁, p₂, . . . p₁ . . . p_M of said threshold means for producing an output R, represented by respective output signals r₁, r₂ . . . r_l . . . r_k, indicative of the particular class of each particular pattern presented to the system.

14. A system as defined in claim 13, wherein said class identifying means comprises a plurality K of OR circuits, there being at least one OR circuit for each class to be identified, each OR circuit being connected to receive those output signals p_i associated with a particular class so as to produce an output signal r_l indicative of said class upon receipt of one or more said output signals p_i.

15. A system as defined in claim 13, wherein said class identifying means comprises:

(a) a plurality of class output means, each of said last-named means being selected to produce outputs indicating events of a single class;

(b) means respectively associated with each of said class output means for selectively activating each of said class output means; and

(c) means responsive to the concurrent activation of a selective activating means and outputs to be produced from the activated class output means.

16. A system as defined in claim 15, wherein each of said class output means is an OR circuit.

17. A system as defined in claim 15 wherein said class identifying means further includes:

(d) means respectively associated with said class output means and actuated in response to the production of an output from said selected class output means for enabling the switching into activation of said class output means without the operation of its associated activating means, whereby said last named class output means can thereafter produce an output in the absence of activation of its associated activating means;

(e) means responsive to the occurrence of outputs from said threshold means not intended as outputs from a currently activated class output means, and outputable from a class output means switchable into activation because of the prior actuation of the enabling means for producing an output from said class output means; and

(f) means responsive to said output from said class output means for selectively feeding back said output to those modifying means whose associated threshold means had produced said not intended outputs to change the value of the modifying factor in those modifying means.

18. A system as defined in claim 17, wherein each of said class output means is an OR circuit.

19. A system as defined in claim 17, wherein said means for causing the outputs from an activated class output means includes a three-input AND circuit while enabled by the concurrent appearance of signals at two of its inputs, the selective activating means being applied to first of its inputs, the output of a threshold means being applied to a second of its inputs, the output of said AND circuit being applied as an input to a said class output means.

20. A system as defined in claim 19, wherein said switching enabling means includes a bistable circuit which is switched to its set state upon the enabling, i.e. the production of an output from said AND circuit, the set output of said circuit being applied to the third of the inputs of said AND circuit.

21. A system as defined in claim 1, wherein the output of a junction element equals the product of its transfer function A_ij and the signal s_j applied thereto.

22. A system as defined in any one of claims 1, 10 and 21, further comprising means for modifying the transfer function A_ij of at least one of said junction elements, when in a training mode, in dependence upon the incoming signal s_j applied thereto and the output signal p'"'"'_i of the summing means i with which said junction element is associated.

23. A system as defined in claim 22, wherein said transfer function modifying means is operative to modify all of said transfer functions.

24. A system as defined in claim 22, wherein said transfer function modifying means modifies the transfer function A_ij in accordance with the formula:

space="preserve" listing-type="equation">A.sub.ij (t)=γ

A.sub.ij (t-1)+η

s.sub.j p'"'"'.sub.i,

where

A_ij (t) is the new transfer function,

A_ij (t-1) is the previous transfer function prior to this modification,

γ

is a decay constant in the range 0≦

γ

≦

1, and

η

is an adjustable learning parameter.

25. A system as defined in claim 22, wherein said transfer function modifying means comprises means for feeding back the output p'"'"'_i of each summing means to the junction elements associated with that summing means.

26. A system as defined in claim 22, further comprising an output bank R, including:

(e) a plurality M of second input terminals, each such terminal (l) adapted to receive one of the M output signals (p_i);

(f) a plurality K of summing means, each summing means (k) having M inputs and an output and being operative to provide a signal (r'"'"'k) at its output representing the sum of the signal representations applied to its inputs; and

(g) a plurality M X K of junction elements, each junction element (kl) coupling one of said second input terminals (l) with one summing means (k) and providing a transfer of information from the respective second input terminal l to the respective summing means k in dependence upon the signal (p_i) appearing at the input terminal and upon the element transfer function B_kl.

27. A system as defined in claim 26, further comprising means for modifying the transfer function B_kl of at least one of the junction elements of the output bank R, when in a training mode, in dependence upon the incoming signal p_i applied thereto and the output signal r_k of the summing means k with which said junction element is associated.

28. A system as defined in any one of claims 1, 10, 21 and 24, further comprising means for modifying the transfer function element A_ij of at least one of said junction elements, when in the training mode, in dependence upon the incoming signal s_j applied thereto and a unit vector of the prototype bank pⁱ, where the j^th component of pⁱ, p_jⁱ, is ##EQU4## whereby δ

A_ij =p_jⁱ s_j.