Electronic thermostat with repetitive operation cycle

• US 4,335,847 A
• Filed: 05/27/1980
• Issued: 06/22/1982
• Est. Priority Date: 05/27/1980
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Michael R. Levine
• Inventors: Levine, Michael R.
• Primary Examiner(s): Wayner, William E.
• Application Number:
  US06/153,343
• Time in Patent Office: 756 Days
• Field of Search: 236/46 R, 236/47, 165/12, 364/410, 364/505, 340/309.1
• US Class Current: 236/46.00R
• CPC Class Codes: F23N 2231/10 for component failures
• CPC Class Codes: F23N 2237/06 two predeterming temperatures, e.g. day-night
• CPC Class Codes: F23N 5/203 using electronic means
• CPC Class Codes: G05D 23/1904 variable in time
• CPC Class Codes: G05D 23/24 the sensing element having a resistance varying with temperature, e.g. a thermistor

Abstract

An electronic multiple-setback thermostat for residential and commercial use includes an internal clock having a week-long cycle. The thermostat is programmed by the operator, usually manually actuable input devices, to control the furnace/air conditioning system to achieve a schedule of temperatures over the weekly period by simply inputting the temperature desired to be attained at the time of entry. Each temperature entry may be programmed to reoccur on a daily basis or to modify the program on a once-a-week basis. The thermostat employs an internal clock which controls memory addresses so that each memory location is representative of a short time period during the weekly cycle. A desired temperature signal is entered in a memory location determined by the clock state at the time of entry and is read out to the control system each time that time state reoccurs. The external temperature sensor employs a thermistor controlled oscillator that is used as the system clock source during failures of the primary power source.

Claims

1. A system for controlling the operative state of a device over a repetitive time period comprising:

a clock operative to generate digital signals representative of the time within the repetitive time period;

a digital memory;

input means for loading digital signals of desired states of the device into the memory;

means for recording the time of entry of each state signal within the repetitive time period; and

means, controlled by the clock for generating state control signals for the device over the repetitive time period, the state control signals being generated at times which are a function of their time of entry into the memory.

2. The system of claim 1 wherein said means for recording the time of entry of each state signal within the repetitive time period comprises means for entering the state of the clock at the time of entry of a desired state signal into the memory along with the state signal.

3. The system of claim 1 wherein the memory is arranged in a plurality of sections, each representative of a particular time period during the repetitive time cycle and said means for recording the time of entry of each state signal within the repetitive time period comprises means for loading a desired state signal into the memory section associated with the time of entry of that signal.

4. The system of claim 3 including means controlled by the clock for sequentially interrogating the memory sections so that a control signal stored in the memory is generated from the memory section at the same time in the repetitive time period that it was entered into the memory.

5. The system of claim 1 in which said input means for loading signals into the memory comprises manually adjustable means for indicating a desired state and a switch positionable in a first position wherein modifications in the desired state are entered into the memory or in a second position wherein modifications of the desired state are not entered into the memory.

6. The system of claim 5 wherein said system is capable of controlling any one of a plurality of devices and including manually operable means for generating a signal representative of the device with which said desired state is associated and for storing said last signal in association with the state signal.

7. The controller 20 of claim 1 wherein the clock output comprises signals representative of time periods within the repetitive time cycle and subperiods within each repetitive time period and including means for recording set point signals in the memory in a first manner in which a recorded set point signal will effect a change in control signal output once during each clock cycle or in a second manner in which each recorded set point will effect a change in the control signal once each period of the clock cycle.

8. An electronic thermostat comprising:

an electronic clock operative to generate signals representative of a repetitive, time cycle;

a memory adapted to store a temperature program for the cycle;

operator actuated control means for entering desired temperature state signals into the memory;

means for storing signals from the clock representative of the time of entry of a desired temperature state with each desired temperature state entered into the memory;

means controlled by the output of the clock for interrogating the memory to derive signals representative of the desired temperature state at a particular time;

means for generating an electricl signal representative of the actual temperature in the environment of the thermostat; and

comparator means for receiving signals representative of the actual temperature and the desired temperature and for generating output control signals.

9. The electronic thermostat of claim 8 wherein said means for storing signals from the clock representative of the time of entry of the desired temperature with each desired temperature state entered into the memory comprises means for associating each of a plurality of sections of the memory with a different state of the clock and means for entering desired temperature state into the memory section associated with the state of the clock at the time of entry of the desired temperature state.

10. The thermostat of claim 8 wherein the memory is divided into seven daily sections and each section is divided into a plurality of subsections.

11. The thermostat of claim 9 further including means for entering a desired temperature state signal either into one section of the memory so that it affects the control mode on a weekly basis, or into each section of the memory so that it affects the control mode on a daily basis.

12. The thermostat of claim 11 wherein said means for entering a desired temperature state signal either into one section of the memory so that it affects the control mode on a weekly basis, or into each section of the memory so that it affects the control mode on a daily basis, is controlled by the clock so that during an initial period of operation of the thermostat a desired temperature state signal is entered into each station of the memory so that it affects the control mode on a daily basis and thereafter a desired temperature state signal is entered into only one section of the memory so that it only affects a control mode on a weekly basis.

13. In a thermostat having a clock operative to generate electrical signals representative of the time in a repetitive cycle, a memory adapted to retain a program of desired temperatures at particular times in the repetitive cycle;

manually operable control means for entering desired temperatures into the memory; and

circuitry for interrogating the memory with the output of the clock to generate signals representative of the desired temperature at a particular time, the improvement comprising;

means for storing the output of the clock at the time a particular desired temperature is entered into the memory in association with the memory signals representative of the desired temperature, whereby the operator need only program the desired temperature at a particular time to allow the system to control generation of that temperature at that particular time each time it reoccurs in the repetitive time cycle.

14. The thermostat of claim 13 wherein said means for storing the output of the clock at the time a particular desired temperature is entered into the memory comprises means for arranging the memory in a plurality of sections, each representative of a particular time period during the repetitive time cycle and means for loading a desired temperature signal into the memory section associated with the time of entry of that signal.

15. The thermostat of claim 14 including means for entering a desired temperature signal either into one section of the memory so that it affects the control mode on a weekly basis, or into each section of the memory so that it affects the control mode on a daily basis.

16. In a process controller, in combination:

a clock operative to generate signals representative of the time within a repetitive time cycle;

operator control means for generating a signal representative of a set point for the process;

a memory operative to record the signal representative of the set point in a manner dependent upon the status of the clock at the time of generation of the set point signal; and

means controlled by the clock for generating output control signals for the process based on the recorded set points and the time of recordation of the set points.

17. The controller of claim 16 wherein said memory constitutes a plurality of separate memory sections each representative of a separate time segment within the repetitive time cycle and the manner of recording the set point in association with the time of change of the set point comprises recording a changed set point in a memory section associated with the time of change of the set point.

18. The controller of claim 17 in which said means for generating control signals as a function of the time within the repetitive time cycle in which said set point changes were recorded consists of means employing the output of the clock as a memory address to output control signals from the memory sections in which they were recorded as a function of the status of the clock.

19. The controller of claim 16 including manually operable control means for modifying the set point signal.

20. The controller of claim 16 including switch means positioned in a first position wherein the control signals generated are based upon set points recorded in the memory and a second position wherein the control signals outputted are a function of the condition of the means for generating signals representative of set points.