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Logic system for selectively reconfiguring an intersystem communication link

  • US 4,370,708 A
  • Filed: 01/07/1980
  • Issued: 01/25/1983
  • Est. Priority Date: 10/31/1978
  • Status: Expired due to Term
First Claim
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1. Intersystem link (ISL) unit architecture wherein an ISL unit may be selectively reconfigured to accommodate information transfers between a local communication bus and any data processing unit including memory units, peripheral control units, central processing units and ISL units in electrical communication with any of plural communication busses in a data processing system wherein each of said plural communication busses are in electrical communication with an ISL unit and ISL units are in electrical communication in pairs, which comprises:

  • (a) cycle control logic means responsive to communication bus requests and to an output control command from a CPU in electrical communication with one of said plural communication busses for transitioning an addressed ISL unit between an on-line logic state and a stop logic state wherein said addressed ISL unit may respond to pending communication bus requests while inhibiting further communication bus requests;

    (b) programmable memory means in electrical communication with said one of said plural communication busses and having memory cell locations for storing binary coded information received from any one of said plural communication busses for accommodating information transfers between said plural communication busses; and

    (c) configuration control logic means responsive to said cycle control logic means for altering binary coded information stored in selected ones of said memory cell locations of said programmable memory means in accordance with configuration data received from said CPU, thereby providing a dynamic reassignment of data processing system resources between said plural communication busses.

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