Addressing of operands within a segment utilizing segment descriptors

• US 4,385,352 A
• Filed: 04/13/1981
• Issued: 05/24/1983
• Est. Priority Date: 05/16/1973
• Status: Expired due to Fees

• Current Assignee: Compagnie Internationale Pour L'Informatique Cii-Honeywell Bull
• Original Assignee: Compagnie Internationale Pour L'Informatique Cii-Honeywell Bull
• Inventors: Bienvenu, Jacques M. J.
• Primary Examiner(s): Springborn, Harvey E.
• Application Number:
  US06/253,879
• Time in Patent Office: 771 Days
• Field of Search: 364/200 MS File
• US Class Current: 711/208
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence

Abstract

A data processing system includes apparatus for addressing operands within a segment utilizing segment descriptors. The apparatus is responsive to instruction words executed by a first of a plurality of processes. An exemplary embodiment includes a first component which stores a segment table containing a plurality of segment descriptors, a plurality of second components, each selectively coupled to the first components and responsive to a selected one of the instruction words, identify the segment table and the location within the segment table and store an offset address within the segment identified by the segment descriptor, a third component is responsive to an address syllable element of an instruction being executed for addressing one of the plurality of second components, a fourth component stores a displacement D from the address syllable, a fifth component is coupled to the second and fourth components for adding the displacement D to the offset whereby an SRA is developed (a segment relative address), a sixth component stores an index for addressing the next sequential word following the currently addressed word and adds the index to the displacement D and to the offset, a seventh component generates an absolute address of an operand contained within the segment and is coupled to the first and fifth components for adding the segment relative address SRA to the base address of the segment descriptor associated with the segment, and an eighth component is coupled to the sixth component for incrementing the absolute address location of the operand to the next word following the currently addressed word.

Claims

1. In an internally programmed data processing apparatus responsive to instruction words being executed by a first of a plurality of processes and having stored therein a plurality of different types of groups of informational data, each data group type associated with an address space bounded by a segment having predetermined bounds, an apparatus for developing the segment relative address (SRA) of an operand contained within any segment comprising:

a first means for storing at least one segment table containing a plurality of segment descriptors having a predetermined format, each of said segment descriptors describing one segment associated with a predetermined one of said segment descriptors, each segment descriptor being accessible only by any number of particular predetermined ones of said plurality of processes to control access rights to said segment, and with each of said segment descriptors containing a base address of its associated segment;

b. a plurality of second means, each selectively coupled to said first means and responsive to a selected one of said instruction words and having a predetermined format for storing a segment number SEG for identifying a segment table and the location of a segment descriptor within said segment table, said second means also for storing an offset address within the segment identified by said segment descriptor, said offset address for locating from said segment base address the first byte of a word within said segment;

c. third means responsive to an address syllable element of an instruction being executed for addressing one of said plurality of second means;

d. fourth means for storing a displacement D from said address syllable, said displacement D for locating from the first byte of said word within said segment any other byte of said word; and

e. fifth means coupled to said second and fourth means for adding said displacement D to said offset whereby said SRA is developed.

2. An apparatus as recited in claim 1, including sixth means for storing an index for addressing the next sequential word following the currently addressed word and responsive to a selected one of said instruction words, said sixth means for adding said index to said displacement D and to said offset.

3. An apparatus as recited in claim 1, including seventh means for generating an absolute address of an operand contained with the segment, said seventh means coupled to said first and fifth means for adding said segment relative address SRA to said base address of said segment descriptor associated with said segment.

4. An apparatus as recited in claim 3, including eighth means coupled to said sixth means for incrementing said absolute address location of said operand to the next word following the currently addressed word.

5. In an internally programmed data processing apparatus including a plurality of base registers, said apparatus being responsive to internally stored instruction words being executed by a first process of a plurality of processes and having stored in said data processing apparatus a plurality of different types of groups of informational data, each data group type associated with an address space bounded by a segment having predetermined bounds, an apparatus for developing by indirection to said base registors the segment relative address (SRA) of an operand contained within any segment comprising:

a. first means for generating the absolute address of a first data descriptor, and first data descriptor containing a base register address element for identifying one of a plurality of said base registers containing first address elements of the address of a first operand to be accessed within said segment, and said data descriptor also providing the second address elements of said first operand to be accessed within said segment said first operand being a second data descriptor;

b. second means for storing at least one segment table containing a plurality of segment descriptors having a predetermined format, each of said segment descriptors describing one segment associated with a predetermined one of said segment descriptors and each of said segment descriptors containing a base address of its associated segment, said predetermined one of said segment descriptors being identified by an element of said address in said base register.

c. third means coupled to said first and second means for generating a segment relative address (SRA) of said first operand from said first and second address elements.

6. The apparatus as recited in claim 5, including fourth means coupled to said second and third means for generating from said SRA and said base address the absolute address of said first operand contained within said segment.

7. The apparatus as recited in claim 5 wherein said first address elements include a segment number SEG and an offset address, said segment number for locating said predetermined one of said segment descriptors in said segment table, and said offset address for addressing said first operand from a base location within said segment said beam location being at the beginning of the boundary of said segment.

8. The apparatus as recited in claim 7, wherein said second address elements include a displacement address, and wherein said first operand comprises a word having a plurality of bytes, said displacement address for locating any byte of said word referenced from the beginning of the first byte of said word.

9. The apparatus as recited in claim 8 wherein said fourth means for generating the segment relative address (SRA) adds said offset address and said displacement address.

10. The apparatus as recited in claim 9, wherein said fourth means for generating the absolute address of said first operand contained within said segment adds said SRA to said base address.

11. In an internally programmed data processing apparatus having a plurality of base registers, said apparatus being responsive to internally stored instructions being executed by a first process of a plurality of processes and having stored within said data processing apparatus a plurality of different types of groups of informational data, each data group type associated with an address space bounded by a segment having predetermined bounds, an apparatus for developing by n indirections to one of said plurality of base registers the segment relative address (SRA) of a final operand word contained within a selected segment comprising:

a. first means for storing a plurality of segment tables, each segment table containing a plurality of segment descriptors, each descriptor having a predetermined format, with predetermined ones of said segment descriptors associated with predetermined segments on a one to one basis, each of said segment descriptors describing its associated segment and each of said segment descriptors containing a base address element of its associated segment, each segment descriptor being accessible only by any number of particular predetermined ones of said plurality of processes to control access rights to said segment, said base address element for locating the base location of the beginning of said associated segment, a predetermined one of said segment descriptors being identified by a first address element stored in one of said base registers;

b. second means selectively coupled to said first means for storing an address syllable of a selected one of said instructions, said address syllable containing a base register address element for identifying one of a plurality of said base registers, said one of said base registers containing a second address element for addressing a first operand word within a first segment from the base location of said first segment, said adddress syllable also containing a first displacement address element for addressing at least one byte of said first operand word, said byte addressed relative to the beginning of the first byte of said first operand word;

c. third means coupled to said first and second means for generating the absolute address of a data descriptor from said second address element, from said first displacement address element and from said base address element, said data descriptor containing a second base register address element for identifying a second of said plurality of base registers containing third address elements of the address of the final operand to be accessed within a second segment, said data descriptor also containing a second displacement address element for addressing at least one byte of a second operand word, said byte addressed relative to the beginning of the first byte of said final operand word; and

d. fourth means responsive to said third address element and to said second displacement address for generating a segment relative address of said final operand from said third address element and said displacement address element.

12. The apparatus as recited in claim 11 wherein said third address element in said second of said plurality of base registers contains a segment number SEG for locating a predetermined second of said segment descriptors associated with said second segment, and wherein said third address element in said second plurality of base registers contains an offset address element for locating the final operand within said second segment relative to the base address of said second segment.

13. The apparatus as recited in claim 12, including fifth means coupled to said offset address element and to said segment reltive address (SRA) for generating an absolute address of the final operand word of said offset address element and said segment relative address of sais final operand.

14. An apparatus as recited in claim 13 wherein said fifth means for generating the absolute address of said final operand word is an adder and whereby said offset is added to said segment relative address (SRA).

15. In an internally programmed data processing apparatus having a plurality of base registers, said apparatus being responsive to internally stored instructions being executed by a first of a plurality of processes and having stored within said data processing apparatus a plurality of different types of groups of informational data, each data group type associated with an address space bounded by a segment having predetermined bounds, an apparatus for developing by n indirections to one of a plurality of segment tables the segment relative address (SRA) of a final operand word contained within a selected segment comprising:

a. a first means for storing a plurality of segment tables, each segment table containing a plurality of segment descriptors, each descriptor having a predetermined format, with predetermined ones of said segment descriptors associated with predetermined segments on a one to one basis, each of said segment descriptors describing its associated segment, each segment descriptor being accessible only by any number of particular predetermined ones of said plurality of processes to control access rights to said segment, and each of said segment descriptors containing a base address element of its associated segment, said base address element for locating the base location of the beginning of said associated segment, a predetermined one of said segment descriptors associated with a first of said segments being identified by a first address element stored in one of said base registers;

b. second means coupled to said first means for storing an address syllable of said instruction, said address syllable containing a base register address element for identifying one of a plurality of said base registers, said one of said base registers containing a second address element for addressing a first operand word within a first segment from the base location of said first segment, said address syllable also containing a first displacement address element for addressing at least one byte of said first operand word, said byte being addressed relative to the beginning of the first byte of said first operand word, said first operand word being a first segment descriptor;

c. third means coupled to said first and second means for generating the absolute address of said first segment descriptor utilizing said second address element, said first displacement address element and said base address element, said first segment descriptor containing a third address element of the address of the final operand to be accessed within a second segment, said first segment descriptor also containing a second displacement address element for addressing at least one byte of said final operand word, said byte addressed relative to the beginning of the first byte of said final operand word; and

d. fourth means responsive to said third address element and said displacement address element for generating a segment relative address (SRA) of said final operand word utilizing said third address element and said second displacement address element.

16. The apparatus as recited in claim 15 wherein said third address element of said data descriptor contains a segment number SEG for locating a predetermined second segment descriptor of said segment descriptors associated with said second segment.

17. The apparatus as recited in claim 16, wherein said first segment descriptor is a direct type data descriptor and said second segment descriptor contains a second base address element of the beginning of said second segment, said apparatus including fifth means responsive to said second displacement address element and said second base address element for generating an absolute address of the final operand word utilizing said second displacement address element and said second base address element of said second segment descriptor.

18. An apparatus as recited in claim 17 wherein said fifth means for generating the absolute address of said final operand word is an adder and whereby said second displacement and said second base address element are added together.

19. The apparatus as recited in claim 18, including indexing means coupled to said adder for indicating the incrementing of the absolute address location of said final operand to the next sequential word following the currently addressed word.

20. The apparatus as recited in claim 18, wherein said indexing means indicates the incrementing of the SRA of said final operand to the next SRA word following the current SRA word.

21. In an internally programmed data processing apparaus having a plurality of first storage means for storing elements of an address of a final operand, said apparatus responsive to instruction words being executed by a first process of a plurality of processes, said first storage means having stored therin a plurality of different types of roups of informatinal data, each data group type associated with an address space bounded by a predetermined segment of a plurality of segments having predetemined bounds, an apparatus for developing an absolute address of said final operand contained within said predetermined segment, said apparatus comprising:

a. first means responsive to a first address element contained within said instruction words and said second address element contained within said first storage means, said first means generating in response to a predetermined one of said first address elements and to a predetermined one of said second address elements a segment relative address (SRA) of said final operand;

b. second means for storing at least one segment table containing a plurality of segment descriptors having a predetermined format, each of said segment descriptors describing one of said plurality of segments, each segment descriptor being accessible only by any number of particular predetermined ones of said plurality of processes to control access rights to said segment, said one segment associated with a predetermined one of said segment descriptors, and each of said segment descriptors containing a base address of its associated segment; and

c. third means coupled to said first and second means for generating from said base address and said segment relative address (SRA) the absolute address of said final operand.

22. The apparatus as recited in claim 21, including indexing means coupled to said third means for indicating the incrementing of the absolute address location of sad final operand to the next sequential word following the currently addressed word.

23. The apparatus as recited in claim 22, including indexing means for indicating the incrementing of the SRA of said final operand to the next SRA word following the current SRA word.

24. In an internally programmed data processing apparatus having a plurality of base registers, said apparatus being response to internally stored instruction words and having stored within said data processing apparatus a plurality of different type of groups of informational data, each data group type associated with an address spaced bounded by a predetermined segment of a plurality of segments having predetermined bounds, the method of developing an absolute address of a final operand contained within said predetermined segment, said method comprising the steps of:

a. accessing a predetermined one of said instruction words to obtain a first address element, acessing a predetermined one of said base registers to obtain a second address element, and combining said first address element with said second address element to form a segment relative address;

b. storing at least one segment table containing a plurality of segment descriptors having a predetermined format, each of said segment descriptors describing one of said plurality of segments, each segment descriptor being accessible only by any number of particular predetermined ones of said plurality of processes to control access rights to said segment, said one segment being associated with a predetermined one of said segment descriptors, and each of said segment descriptors containing a base address of its associated segment; and

c. combining said base address with said segment relative address (SRA) to form the absolute address of said final operand.

25. The method as recited in claim 24 including the step of indexing on the absolute address location by incrementing the absolute address location of said final operand to the addess next sequential used following the currently addressed word.

26. The method as recited in claim 24 including the step of indexing on the segment relative address (SRA) by incrementing the SRA of said final operand to the next SRA word following the current SRA word.

27. In an internally programmed data processing apparatus having a plurality of base registers, said apparatus being responsive to internally stored instruction words and having stored wthin said data processing apparatus a plurality of different types of groups of informational data, each data group type associated with an address spaced bounded by a predetermined segment of a plurality of segments having predetermined bounds, the method of developing, by n indirections to one of said plurality of base registers, an absolute address of a final operand contained within one of said segments, said method comprising the steps of:

a. accessing a predetermined one of said instruction words to obtain a first address element, accessing a predetermined one of said base registers to obtain a second address element, and combining said first address element with said second address element to form a first segment relative address;

b. storing at least one segment table containing a plurality of segment descriptors having a predetermined format, each of said segment descriptors describing one of said plurality of segments, each segment descriptor being accessible only by any number of particular predetermined ones of said plurality of processes to control access rights to said segment, said one segment being associated with a predetermined one of said segment descriptors, and each of said segment descriptors containing a base address of its associated segment;

c. accessing a predetermined one of said segment descriptors to obtain a first base address, and combining said first base address with said first segment relative address (SRA) to form the absolute address of a data descriptor;

d. accessing said data descriptor to obtain a third address element, accessing a predetermined second of said base registers to obtain a third address element, and combining said third address element with said fourth address element to form a second segment relative address (SRA); and

e. accessing a predetermined second of said segment descriptors to obtain a second base address, and combining said second base address with said second segment relative address (SRA) to form a second absolute address of the final operand.

28. The method as recited in claim 27 including the step of indexing on the second absolute address location by incrementing the second absolute address location of said final operand to the address of the next sequential word following the currently addressed word.

29. The method as recited in claim 28 including the step of indexing on the second segment relative address (SRA) by incrementing the second SRA of said final operand to the next SRA following the current SRA word.