Microprocessor with compressed control ROM

• US 4,402,043 A
• Filed: 11/24/1980
• Issued: 08/30/1983
• Est. Priority Date: 11/24/1980
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Laws, Gerald E., Guttag, Karl M., McDonough, Kevin C.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US06/209,915
• Time in Patent Office: 1,009 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 365/200
• US Class Current: 712/37
• CPC Class Codes: G06F 15/7839 with memory
• CPC Class Codes: G06F 9/223 Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
• CPC Class Codes: G06F 9/3814 Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
• CPC Class Codes: G11C 17/12 using field-effect devices

Abstract

A single-chip microprocessor device of the MOS/LSI type contains an ALU, several interal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. The control ROM is an array of rows and columns of potential MOS transistors. This ROM is compressed by eliminating column lines which contain no transistors, and eliminating column decode circuitry associated with such column lines. The number of lines which can be eliminated is increased by reducing the number of row lines (thereby lengthening the row lines) and selecting default conditions of controls (by inverting some outputs) to increase the number of vacant positions in the ROM.

Claims

1. A decoder comprising a plurality of cell groups;

each cell group including;

an array of potential cells with M rows and N columns,

first selector means for activating one of said M rows as defined by an address of B bits,

second selector means for selecting one of said N columns as defined by an address of C bits,

where M equals 2^B, and

wherein logically unneeded columns of potential cells are physically omitted from the array, whereby N is an integer substantially less than 2^c ;

and the cell groups contain differing numbers N of columns.

2. A decoder according to claim 1 wherein the potential cells are field effect transistors.

3. A decoder according to claim 2 wherein the second selector means for each cell group is an array of 2^c rows and N columns.

4. A decoder according to claim 3 wherein each said array is populated with potential cells using false logic.

5. A logic array for generating a plurality of control signals for microprocessor device comprising:

a plurality of row lines and means for selecting one of said row lines for activation in response to an address,

a plurality of separate groups of column lines intercepting said row lines to provide an array, the column lines of each group generating a separate one of said control signals, and means for selecting no more than one column line in each group for activation in response to an address, the number of column lines per group differing among the groups, the total number of column lines in the groups being substantially greater than the number of said row lines.

6. A logic array according to claim 5 wherein a potential cell is provided at the intersection of each row line and each column line.

7. A logic array according to claim 6 wherein the potential cells are insulated gate field effect transistors.

8. A logic array according to claim 6 wherein there is at least one cell on each column line in each group.

9. A logic array according to claim 8 wherein the means for selecting column lines activates a column line in some but not all of said groups for a given address.

10. A logic array according to claim 9 wherein the maximum number of column lines in a group does not exceed N and said given address contains C bits, where N=2^c.

11. A method of making a logic array of rows and columns of potential cells for generating a plurality of control signals for a microprocessor device, comprising the steps of:

defining a plurality of groups of equal numbers of said columns, one group for each control signal, the columns in each group intercepting said rows at said potential cells,

providing row select means for activating one row in response to a first part of an address,

providing column select means for activating no more than one column in each group in response to a second part of an address,

physically eliminating from the array columns which contain no cells for a given sequence of control signals to be generated for the microprocessor device whereby each column in every group contains at least one of said cells.

12. A method according to claim 11 including the step of eliminating parts of said column select means for the columns containing no cells.

13. A method according to claim 12 wherein some of the groups contain unequal numbers of columns after eliminating the columns which contain no cells.

14. A method according to claim 13 including the step of forming an insulated gate field effect transistor at the location of each one of the potential cells for which a control signal is to be generated for a given first and second address.

15. A method according to claim 14 wherein said addresses are selected to maximize the number of columns containing no cells.

16. A method of making a logic array of rows and columns of potential cells for generating a plurality of control signals for a microprocessor device comprising the steps of:

defining a plurality of equal groups of said columns, one group for each control signal, the columns intercepting said rows at said potential cells,

providing row select means for activating one row in response to a first address,

providing column select means for activating no more than one column in each group in response to a second address,

eliminating columns which contain no cells for a given sequence of control signals to be generated for the microprocessor device,

including the step of populating the array with cells using false logic to thereby increase the number of columns containing no cells.

17. A method of making a logic array of rows and columns of potential cells for generating a plurality of control signals for a microprocessor device comprising the steps of:

defining a plurality of equal groups of said columns, one group for each control signal, the columns intercepting said rows at said potential cells,

providing row select means for activating one row in response to a first address,

providing column select means for activating no more than one column in each group in response to a second address,

eliminating columns which contain no cells for a given sequence of control signals to be generated for the microprocessor device,

including the step of inverting said control signals to thereby increase the number of columns containing no cells.

18. A microprocessor system comprising:

a memory containing a large number of locations defined by addresses and containing program instructions and data,

input/output means for receiving and transmitting information,

a central processing unit coupled to said memory and said input/output means by conductor means to transfer addresses, program instructions, data and information between the memory, input/output means and central processing unit,

logic array means in said central processing unit for receiving representations of said program instructions for decoding and generating control signals to define operation of the system, the logic array means including

a plurality of rows and columns of potential cells, the columns arranged in a plurality of groups of columns, each group corresponding to one of the control signals, selector means to select rows and columns in response to one of said program instructions, the number of columns in a group differing among the groups and all columns having at least one cell whereby no columns are unused, the total number of columns greatly exceeding the number of rows.

19. A system according to claim 18 wherein the cells are insulated gate field effect transistors.

20. A system according to claim 19 wherein the central processing unit is formed in a single semiconductor integrated circuit.