Digital counter/transmitter with remote receiver/display

• US 4,408,204 A
• Filed: 08/06/1980
• Issued: 10/04/1983
• Est. Priority Date: 08/06/1980
• Status: Expired due to Term

• Current Assignee: Midwest Computer Register Corporation
• Original Assignee: Midwest Computer Register Corporation
• Inventors: Salvesen, Richard S.
• Primary Examiner(s): Groody, James J.
• Application Number:
  US06/175,857
• Time in Patent Office: 1,154 Days
• Field of Search: 340/870.02, 340/870.03, 340/870.24, 340/870.19, 340/870.2, 340/870.22, 377/37, 377/44
• US Class Current: 340/870.24
• CPC Class Codes: G08C 19/28 using pulse code

Abstract

A digital counter receives pulses from a transducer monitoring gasoline pumped, articles moving along an assembly line, count processes in batch controlled systems, or the like. The counter stores four decades of BCD encoded data. The counter is continuously scanned and the data converted digit by digit into a serial stream of pulse width modulated bursts containing the BCD data for each digit accompanied by its associated address in the counter. The receiver operates in the reverse of the transmitter. Each incoming pulse rising edge triggers two pulse generators. If the first pulse generator times out prior to the received pulse, the received pulse will be clocked into a shift register. The second pulse generator is continuously reset during receipt of a sequence of digits. When the second pulse generator times out, the contents of the shift register is latched into a display controller. The receiver distinguishes between individual pulses and consecutive decades by the time delay between received pulses. An "off" pulse generator is provided for inhibiting data bit transmission for a first predetermined time between individual pulses of a decade and an "interdecade" pause generator is provided for inhibiting transmission of data bits of consecutive decades to produce a time delay between decades.

Claims

1. An asynchronous system for remotely monitoring a counted total and locally displaying that total, said system comprising:

counter means for receiving input pulses and maintaining a stored count of said received pulses as data in counter elements;

scanning means for sequentially accessing data in each element of said counter means;

address counter means for assigning an address to data from each said element indicative of the position of the element containing the addressed data relative to the other elements in said counter means;

pulse width modulator means for receiving data from each element of said counter means when accessed by said scanning means and the assigned address and pulse width modulating said data and assigned address;

transmitter means for receiving said pulse width modulated data and assigned address and transmitting pulses in response thereto;

receiving means for receiving said pulses;

discriminator means for converting said pulses into discrete amplitude signals indicative of said data and assigned addresses; and

display and control means for displaying said discrete amplitude signals indicative of said data in accordance with the assigned address.

2. The invention as defined in claim 1 wherein said counter means comprises a multi-decade counter with each of said elements comprising one decade of said counter and in which the output signal of each decade comprises bits of information outputted in parallel form in response to a given element being accessed by said scanning means.

3. The invention as defined in claim 2 and further including a parallel to serial converter for receiving said parallel bits and outputting said bits in serial form, and wherein said transmitter means is operative to transmit individual data bits.

4. The invention as defined in claim 3 wherein said scanning means includes a bit counter means for counting bits of data transmitted by said transmitter means and sequencing said counter means when all bits of a single decade have been transmitted.

5. The invention as defined in claim 4 and further including an off pulse generator means responsive to transmitted data bits for inhibiting data bit transmission for a first predetermined time between data bits.

6. The invention as defined in claim 5 and further including an interdecade pause generator for inhibiting transmission of data bits for a second predetermined time after all bits of a single decade have been transmitted.

7. The invention as defined in claim 4 and wherein said address counter means outputs a signal indicative of the significance of an associated decade output of said counter means, said address counter being operatively connected to said bit counter means for sequencing thereby.

8. The invention as defined in claim 7 wherein said address counter means includes a parallel output operatively connected to said pulse width modulator means.

9. An asynchronous system for remotely monitoring a counted total and locally displaying that total, said system comprising:

counter means for receiving input pulses and maintaining a stored count of said received pulses as data in counter elements;

scanning means for sequentially accessing data in each element of said counter means;

address counter means for assigning an address to data from each said element indicative of the position of the element containing the addressed data relative to the other elements in said counter means;

modulator means for receiving data from each element of said counter means when accessed by said scanning means and the assigned address and modulating said data and assigned address;

transmitter means for receiving said modulated data and assigned address and transmitting pulses in response thereto;

receiving means for receiving said pulses;

discriminator means for converting said pulses into discrete amplitude signals indicative of said data and assigned addresses; and

display and control means for displaying said discrete amplitude signals indicative of said data in accordance with the assigned address

wherein said discriminator means includes a reference pulse generator means operative to emit a reference pulse upon receipt of one of said received pulses; and

comparator means for comparing the duration of said reference pulse to said the duration of received pulse.

10. The invention as defined in claim 9 wherein said comparator means comprises a shift register having a shift input for receiving said reference pulse and a data input for receiving said received pulse.

11. The invention as defined in claim 10 and further including a missing pulse detector means for measuring the time lapse between received pulses.

12. The invention as defined in claim 11 wherein said display and control means is operatively connected to said missing pulse detector means and to said shift register for displaying an updated signal in response to the spacing between received pulses being greater than a predetermined time.

13. The invention as defined in claim 12 wherein said missing pulse detector means comprises a retriggerable pulse generator.

14. An asynchronous system for remotely monitoring a counted total and locally displaying that total, said system comprising:

counter means for receiving input pulses and maintaining a stored count of said received pulses in binary coded decimal format containing a plurality of digits;

scanning means for individually accessing each digit of said counter means;

address means for assigning an address to each digit accessed by said scanning means;

modulation means for modulating each digit and assigned address;

transmitter means for transmitting each modulated digit and assigned address;

receiver means for receiving each modulated digit and assigned address;

demodulation means for demodulating each received digit and assigned address; and

display means for displaying each digit in accordance with the assigned address such that each digit is displayed relative to other digits in a position determined by the assigned address.

15. The system of claim 14, wherein each digit comprises a group of bits, and said transmitter means comprises means for transmitting each bit with a first predetermined space between bits of a single digit and with a second spacing between groups of bits of different digits.

16. The system of claim 15 wherein said modulation means pulse width modulates each bit of each digit with pulses having a first width to indicate bits having a first value and pulses having a second width to indicate bits having a second value, and said demodulation means includes a shift register having a data input connected to receive said pulse width modulated bits, a pulse generator connected to receive said modulated bits and outputting a pulse having a width intermediate said first and second widths in response to each bit, said shift register having a shift input connected to receive the pulses outputted from said generator, whereby said intermediate width pulses cause said shift register to enter a first value from said data input in response to said first width pulse timing out prior to said intermediate width pulse, or a second value in response to said intermediate width pulse timing out prior to said second width pulse.