Signal processing system

• US 4,408,284 A
• Filed: 01/19/1981
• Issued: 10/04/1983
• Est. Priority Date: 01/19/1981
• Status: Expired due to Fees

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Kijesky, Michael M., Bogle, Charles T.
• Primary Examiner(s): Ruggiero, Joseph F.
• Application Number:
  US06/227,025
• Time in Patent Office: 988 Days
• Field of Search: 364/484, 364/485, 364/572, 364/724, 364/725, 364/726, 328/165, 328/166, 328/167, 328/155, 324/77 B, 324/78 D, 324/77 E, 324/78 F, 324/78 Z
• US Class Current: 702/77
• CPC Class Codes: G06F 18/00 Pattern recognition
• CPC Class Codes: G06F 2218/12 Classification; Matching

Abstract

A signal processing system and technique is disclosed for detecting the pence of a desired frequency signal particularly that of a sine wave, in a noisy environment. The signal mixed with noise is received and analyzed by a Fast Fourier Transform spectrum analyzer the output of which is indicative of instantaneous signal phase. The output of the spectrum analyzer is digitally processed to produce a series of average instantaneous signal values based upon the instantaneous signal phase and a statistical estimate of its rate of change, the values being representative of the relative signal strengths for a progression of phase reference values between 0° and 360°. The desired signal is detected when an average instantaneous signal value exceeds a threshold value determined empirically based upon a certain probability of detection and false alarm rate.

Claims

1. A system for detecting the presence of a desired signal frequency in a multi-signal environment, comprising:

spectrum analyzer means adapted to sample the multi-signal environment for providing digital information indicative of real and imaginary magnitude components of the desired signal frequency;

phase determinator means connected to receive the digital information from said spectrum analyzer means for producing a first digital signal indicative of the instantaneous phase of the desired signal frequency;

phase precession means connected to said phase determinator means for producing a second digital signal representative of a statistical estimate of phase variation of the desired signal frequency;

a first fixed storage device adapted to provide a plurality of third digital signals representative of distinct phase reference values between 0° and

360°

;

an adder connected to said phase precession means and said first fixed storage device for summing the second digital signal with each of the plurality of third digital signals thereby producing a plurality of fourth digital signals representative of revised phase reference values;

cosine integrator means connected to said phase determinator means and said adder for producing a plurality of fifth digital signals representative of relative signal strength for each of the phase reference values;

a second fixed storage device adapted to provide a sixth digital signal representative of a threshold signal value; and

a comparator connected to said cosine integrator means and said second fixed storage device for indicating the presence of the desired signal frequency when any of the plurality of fifth digital signals exceeds the sixth digital signal.

2. A signal detection system according to claim 1, wherein said phase determinator means comprises:

a pair of registers connected in parallel to said spectrum analyzer means for holding digital information indicative of real and imaginary magnitude components of the desired signal frequency; and

functional divider means connected to said pair of digital registers for performing an inverse tangent operation on the quotient of the imaginary and real magnitude components.

3. A signal detection system according to claim 1, wherein said phase precession means comprises:

a pair of registers connected in series of said phase determinator means for storing successively produced first digital signals;

a subtractor connected to each of said pair of registers for producing a digital output signal indicative of a change in the instantaneous phase of the desired signal frequency;

a recirculating adder coupled to said subtractor for summing the digital output signals thereof; and

a normalizer connected to said recirculating adder for producing the second digital signal.

4. A signal detection system according to claim 1, wherein said cosine integrator means comprises:

a subtractor connected to said phase determinator means and said adder for subtracting each of the plurality of fourth digital signals from the first digital signal thereby producing a plurality of phase differential outputs;

a read-only memory coupled to said subtractor and stored with cosine values for producing a plurality of cosine output signals, each cosine output signal corresponding to one of the plurality of phase differential outputs; and

an integrator connected to said read-only memory for integrating each of the plurality of cosine output signals over a time period.

5. A signal detection system according to claim 4, wherein said first and second fixed storage devices are read-only memories.

6. A signal detection system according to claim 5, wherein said spectrum analyzer means is a Fast Fourier Transform Spectrum analyzer.

7. A signal processor for detecting the presence of a desired signal frequency in a multi-signal environment sampled by a Fast Fourier Transform spectrum analyzer, comprising:

phase determinator means connected to the spectrum analyzer for producing a first digital signal indicative of the instantaneous phase of the desired signal frequency;

phase precession means connected to said phase determinator means for producing a second digital signal representative of a statistical estimate of phase variation of the desired signal frequency;

a first fixed storage device adapted to provide a plurality of third digital signals representative of distinct phase reference values between 0° and

360°

;

an adder connected to said phase precession means and said first fixed storage device for summing the second digital signal with each of the plurality of third digital signals thereby producing a plurality of fourth digital signals representative of revised phase reference values;

cosine integrator means connected to said adder for producing a plurality of fifth digital signals representative of relative signal strength for each of the phase reference values;

a second fixed storage device adapted to provide a sixth digital signal representative of a threshold signal value; and

a comparator connected to said cosine integrator means and said second fixed storage device for indicating the presence of the desired signal frequency when any of the plurality of fifth digital signals exceeds the sixth digital signal.

8. A signal processor according to claim 7, wherein said phase determinator means comprises:

a pair of registers connected in parallel to said spectrum analyzer means for holding digital information indicative of real and imaginary magnitude components of the desired signal frequency; and

functional divider means connected to said pair of digital registers for performing an inverse tangent operation on the quotient of the imaginary and real magnitude components.

9. A signal processor according to claim 7, wherein said phase precession means comprises:

a pair of registers connected in series to said phase determinator means for storing successively produced first digital signals;

a subtractor connected to each of said pair of registers for producing a digital output signal indicative of a change in the instantaneous phase of the desired signal frequency;

a recirculating adder coupled to said subtractor for summing the digital output signals thereof; and

a normalizer connected to said recirculating adder for producing the second digital signal.

10. A signal processor according to claim 7, wherein said cosine integrator means comprises:

a subtractor connected to said phase determinator means and said adder for subtracting each of the plurality of fourth digital signals from the first digital signal thereby producing a plurality of phase differential outputs;

a read-only memory coupled to said subtractor and stored with cosine values for producing a plurality of cosine output signals, each cosine output signal corresponding to one of the plurality of phase differential outputs; and

an integrator connected to said read-only memory for integrating each of the plurality of cosine output signals over a time period.

11. A signal processor according to claim 10, wherein said first and second fixed storage devices are read-only memories.