Column and row erasable EEPROM

• US 4,408,306 A
• Filed: 09/28/1981
• Issued: 10/04/1983
• Est. Priority Date: 09/28/1981
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Kuo, Clinton C. K.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/306,120
• Time in Patent Office: 736 Days
• Field of Search: 365/189, 365/218, 365/230
• US Class Current: 365/185.33
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/32 Timing circuits

Abstract

An EEPROM has an array of memory elements arranged by row and column which is accessed by a decoder capable of selecting all columns while enabling a single row in response to one input and selecting one column while enabling all rows in response to another input, thereby selectively erasing one entire row or column.

Claims

1. An electrically erasable programmable read only memory (EEPROM) comprising:

an array of electrically erasable memory elements arranged with one of said memory elements at the intersection of each of a plurality of rows and columns of said array;

logic means for generating, in response to a row erase mode signal, a row control signal at a first logic state and a column control signal at a second logic state;

column select means for coupling, when the column control signal is at the second logic state, an erase signal to all of the columns of said array; and

row decoder means for enabling, when the row control signal is at the first logic state, said erase signal to electrically erase the memory elements comprising the row of said array selected in response to a row address signal.

2. The EEPROM of claim 1 wherein the column select means comprises:

a plurality of column address buffer means, each column address buffer means providing two buffered address signals, one true and one complementary, of an individual column address signal when the column control signal is at a first logic state, and providing both buffered address signals at a predetermined logic state when the column control signal is at said second logic state; and

column decoder means for coupling said erase signal to all of the columns of said array in response to all of the buffered address signals of the plurality of column address means being at said predetermined logic state.

3. An electrically erasable programmable read only memory (EEPROM) comprising:

an array of electrically erasable memory elements arranged with one of said memory elements at the intersection of each of a plurality of rows and columns of said array;

logic means for generating in response to a column erase mode signal a column control signal at a first logic state and a row control signal at a second logic state;

row select means for coupling, when the row control signal is at the second logic state, an erase signal to all of the rows of said array; and

column decoder means for enabling, when the column control signal is at the first logic state, said erase signal to electrically erase the memory elements comprising the column of said array selected in response to a column address signal.

4. The EEPROM of claim 3 wherein the row select means comprises:

a plurality of row address buffer means, each row address buffer means providing two buffered address signals, one true and one complementary, of an individual row address signal when the row control signal is at a first logic state, and providing both buffered address signals at a predetermined logic state when the row control signal is at said second logic state; and

row decoder means for coupling said erase signal to all of the rows of said array in response to all of the buffered address signals of the plurality of row address means being at said predetermined logic state.