Ordering system for pairing feature intersections on a simulated radar sweepline

• US 4,414,643 A
• Filed: 05/15/1981
• Issued: 11/08/1983
• Est. Priority Date: 05/15/1981
• Status: Expired due to Fees

• Current Assignee: L-3 Communications Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Singer PLC (Hayleys Plc)
• Inventors: Meyer, Jerome W.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US06/263,846
• Time in Patent Office: 907 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/456, 434/1, 434/2
• US Class Current: 345/440
• CPC Class Codes: G09B 9/54 Simulation of radar G09B9/40 takes precedence

Abstract

The disclosure describes a system for ordering and pairing feature boundary intersections on a sweepline of a simulated digital radar visual display screen in order to arrange a variable length list of data in accordance with a desired order. This ordering and pairing system resolves the correct range order of the intersection pairs for any closed feature shape regardless of boundary convexity, range inaccuracy or possible shape anomalies. The system includes an input data control means (11) having one input connection and a plurality of output connections (14, 16, 18) to store the input data temporarily. There is described two sorting pipelines (12, 13) connected to two of the output connections to receive certain described "key" data in order to sort the data in each respective pipeline in accordance with a desired correct relationship of ranges. A temporary storage means (19) is connected to receive the "non-key" data. Finally, a merge logic circuit (32) receives the outputs from the two pipelines (12, 13) and attaches to each of the "key" data that appropriate "non-key" data.

Claims

1. An ordering and pairing system for pairing feature intersections on a sweepline of a simulated radar visual display screen, regardless of shape, orientation and convexity, to arrange a variable length list of data in accordance with a desired correct order, comprising:

input data control circuit means having one input connection means to receive and to store temporarily all of said input data, and having three output connection means;

one of said three output connection means being connected to receive data that has been divided out of all said input data in accordance with a first predetermined characteristic to represent "non-key" data;

two sorting pipeline circuit means to receive "key" data that has been divided out in accordance with a second predetermined characteristic for sorting and arranging the "key" data in each of said two sorting pipeline circuit means in accordance with a desired correct relationship of ranges;

circuit means connected with one of said three output connection means from said data control circuit means to store temporarily that data divided out of all said input data which is associated with range information but which represents "non-key" data; and

merge logic circuit means having three input connections means, one for receiving "key" data from each of said two sorting pipeline circuit means and one for receiving "non-key" data associated with range data from said temporary storage circuit means, and having one output connection means for all of said input data which is now arranged and paired in accordance with said desired correct relationship of ranges.

2. An ordering and pairing system as set forth in claim 1 wherein said second predetermined characteristic is in the form of an additional bit of information associated with said input data as an identification flag.

3. An ordering and pairing system as claimed in claim 2, wherein said identification flag serves to identify boundary entrance range key data and boundary exit range key data.

4. An ordering and pairing system as claimed in claim 1 wherein said two sorting pipeline circuit means are connected to separate and distinct ones of said three output connections means from said control circuit means.

5. An ordering and pairing system as claimed in claim 4 wherein each of said two sorting pipeline circuit means includes data storage means to receive and to store temporarily said data that has been divided out of all said input data in said control circuit means.

6. An ordering and pairing system as claimed in claim 5 including sorting circuit means connected in each respective pipeline circuit means to receive the data stored temporarily in each respective data storage means to perform said range key sorting function.

7. An ordering and pairing system as claimed in claim 6 wherein said sorting circuit means is adapted to perform said sorting function on items of data in each respective pipeline, buffer data storage means connected in each respective pipeline circuit means to receive a first N items of data sorted by each respective sorting circuit means, and bypass connection means around said buffer storage means.

8. An ordering and pairing system as claimed in claim 7 including a second pass sorting circuit means connected in each of said two pipeline circuit means with two input terminals, each of said second pass sorting circuit means is adapted to perform said sorting functions on 2N items of data in each respective pipeline, one of said two input terminals be connected to the output of said buffer data storage means, and the other one of said two input terminals being connected to receive a second N item, where the total number of such items of data is limited to not more than 2N.

9. An ordering and pairing system as claimed in claim 8 including means to connect the output of each of the two respective second pass sorting circuit means to a different one of said two input connection means on said merge logic circuit means, wherein said merge logic circuit means is adapted to accept and correctly pair said entrance range and exit range data, and output data storage means connected to the output terminal of said merge logic circuit means to store temporarily the output data from said merge logic circuit means.