Semiconductor memory device test apparatus
First Claim
1. An apparatus for testing a memory device, comprisinga pattern generator for generating and supplying test patterns to the memory device, including address patterns for accessing the addresses of the memory device,expected value pattern generating means for providing expected data which is expected to correspond to data stored in each respective address of the memory device, in correspondence with the generation of addresses of said address patterns,a comparison circuit for reading out the memory device, for comparing the respective data read out from the memory device and the respective expected data, and for outputting a disagreement signal when the read-out data and the expected data do not agree as defect data of the respective address of the memory device, in correspondence with the generation of addresses of said address patterns,a fault-address memory comprising means for being accessed to read out the content of the respective address thereof, and for subsequently writing any respective defect data that is outputted from said comparison circuit into the same corresponding address, in correspondence with said generation of addresses of said address patterns,a counter for counting the number of said defect data outputted from said comparison circuit,means for inhibiting said counting of said counter when said output from said fault-address memory is a previously stored defect data corresponding to the same respective address of said memory device, andfault signal generating means for generating a fault signal to stop said generation of test patterns when the number counted by said counter exceeds a predetermined value.
2 Assignments
0 Petitions
Accused Products
Abstract
A memory device under test is accessed by an address generated by a pattern generator to write therein data and to read the data out to be compared with expected data, and the comparison result is stored in the fault-address memory by the same address after reading out therefrom the content of the address. When a disagreement is detected through the comparison, it is counted; however, the count operation is inhibited if the data read out from the fault-address memory is a fault data. When the counted number exceeds a predetermined value, a fault signal is generated. After the test is terminated, an address counter is operated, the fault-address memory is read out by the content of the address counter, and when fault data is detected from the output read out, the content of the address counter is fetched into the CPU.
100 Citations
14 Claims
-
1. An apparatus for testing a memory device, comprising
a pattern generator for generating and supplying test patterns to the memory device, including address patterns for accessing the addresses of the memory device, expected value pattern generating means for providing expected data which is expected to correspond to data stored in each respective address of the memory device, in correspondence with the generation of addresses of said address patterns, a comparison circuit for reading out the memory device, for comparing the respective data read out from the memory device and the respective expected data, and for outputting a disagreement signal when the read-out data and the expected data do not agree as defect data of the respective address of the memory device, in correspondence with the generation of addresses of said address patterns, a fault-address memory comprising means for being accessed to read out the content of the respective address thereof, and for subsequently writing any respective defect data that is outputted from said comparison circuit into the same corresponding address, in correspondence with said generation of addresses of said address patterns, a counter for counting the number of said defect data outputted from said comparison circuit, means for inhibiting said counting of said counter when said output from said fault-address memory is a previously stored defect data corresponding to the same respective address of said memory device, and fault signal generating means for generating a fault signal to stop said generation of test patterns when the number counted by said counter exceeds a predetermined value.
-
5. An apparatus for testing a memory device, comprising
a pattern generator for generating and supplying test patterns to the memory device, including address patterns for accessing the memory device, expected value pattern generating means for generating expected data corresponding to the data that is expected to be stored at the respective address in said memory device, in correspondence with the generation of said address patterns, a comparison circuit for comparing the data read out from said memory device with said expected data, for detecting each disagreement therebetween and for outputting a respective disagreement signal as defect data corresponding to a fault at the respective address of said memory device, in correspondence with said generation of addresses of said address patterns, a fault-address memory for storing said defect data output from said comparison circuit at the addresses corresponding to the defective addresses of said memory device, in correspondence with said generation of address of said address patterns, an address counter for generating addresses for reading out said fault-address memory, defect data detecting means for detecting each one of said defect data that is read out from said fault-address memory, address counter control means for advancing said address counter in one direction in response to an access command, and for stopping the advancement of said address counter in response to the detection of each said defect data by said fault data detecting means, and a control section for selectively accessing said fault-address memory by generating said access command for said address counter control means, for determining that said address counter control means has stopped as a result of detecting one of said defect data, and for fetching therein the content of said address counter corresponding to each said stopping of the address counter.
Specification