System for overlaying a computer generated video signal on an NTSC video signal

• US 4,425,581 A
• Filed: 04/17/1981
• Issued: 01/10/1984
• Est. Priority Date: 04/17/1981
• Status: Expired due to Term

• Current Assignee: Corporation For Public Broadcasting
• Original Assignee: Corporation For Public Broadcasting
• Inventors: Siegl, Hermann K., Schweppe, Darrell L.
• Primary Examiner(s): Richardson, Robert L.
• Application Number:
  US06/255,039
• Time in Patent Office: 998 Days
• Field of Search: 358/141, 358/148, 358/146, 358/150, 358/152, 358/160, 358/183, 358/185, 358/182, 358/903, 358/181, 358/139, 358/140, 358/149, 364/514, 364/515, 364/518, 364/521, 340/721, 340/744, 340/747, 340/734, 340/748
• US Class Current: 348/510
• CPC Class Codes: H04N 9/76 for mixing of colour signals H04N9/75 takes precedence

Abstract

A system for overlaying a computer generated video signal on an NTSC video signal includes horizontal and vertical pulse processor circuits for generating a horizontal start signal and a vertical reset signal, respectively, in accordance with NTSC standards, and a clocking system for receiving the vertical reset signal and the horizontal start signal and for generating control signals to control the read out of video data from the video generator of a computer so that it is read out at an NTSC rate. The system further includes a video insert keyer circuit for combining the NTSC video signal and the computer generated video signal and for generating a composite video signal for transmission to a monitor or standard television.

Claims

1. A system, operatively connected to a computer for providing a computer video signal, for overlaying the computer video signal on an NTSC video signal, comprising:

first means for providing the NTSC video signal;

second means, operatively connected to said first means, for receiving the NTSC video signal and for generating a vertical reset signal and a horizontal start signal;

third means, operatively connected to said second means, for generating a clock control signal in dependence upon the horizontal start signal;

a clock, operatively connected to said third means, for generating a clock signal in dependence upon the clock control signal;

fourth means, operatively connected to said clock, said second means and the computer, for generating control signals for controlling the read out of the computer video signal by the computer, the control signals being generated in dependence upon the clock signal and the vertical reset signal;

fifth means, operatively connected to said first means and to the computer, for receiving the NTSC video signal and the computer video signal, and for generating a composite video signal.

2. A system as set forth in claim 1, wherein said second means comprises:

a sync separator circuit, operatively connected to said first means, for receiving the NTSC video signal and for providing, as an output, a sync signal;

a vertical pulse processor circuit, operatively connected to said sync separator circuit and to said fourth means, for receiving the sync signal and for generating the vertical reset signal; and

a horizontal pulse processor circuit, operatively connected to said sync separator circuit and to said third means, for receiving the sync signal and for generating the horizontal start signal.

3. A system as set forth in claim 2, wherein said sync separator circuit comprises:

an amplifier, operatively connected to said first means, for amplifying the NTSC video signal;

means for providing a first half level reference signal; and

a first comparator, operatively connected to said amplifier and said means for providing the first half level reference signal, for generating the sync signal.

4. A system as set forth in claim 3, wherein said vertical pulse processor circuit comprises:

a ramp generator, operatively connected to said first comparator, for generating a sawtooth signal;

means for providing a three forths level reference signal;

a second comparator, operatively connected to said means for providing the three forths level reference signal and to the ramp generator, for generating a vertical sync signal;

a first one-shot multivibrator, operatively connected to said second comparator, for generating a first monostable signal;

a second one-shot multivibrator, operatively connected to said first one-shot multivibrator, for generating a second monostable signal having a variable pulse width; and

a first differentiator, operatively connected to said second one-shot multivibrator and to said fourth means, for generating the vertical reset signal.

5. A system as set forth in claim 3 or 4, wherein said horizontal pulse processor circuit comprises:

a third one-shot multivibrator, operatively connected to said first comparator, for generating a third monostable signal;

a fourth one-shot multivibrator, operatively connected to said third one-shot multivibrator, for generating a fourth monostable signal having a variable pulse width; and

a second differentiator, operatively connected to said fourth one-shot multivibrator and to said third means, for generating the horizontal start signal.

6. A system as set forth in claim 2, wherein said fourth means comprises a video divider chain, operatively connected to said third means, said clock, said vertical pulse processor circuit and the computer, said video divider chain generating and transmitting a clock stop signal to said third means, said video divider chain further generating a character repetition signal, said system further comprising a space control circuit, operatively connected between said video divider chain and said third means, for receiving said character repetition signal and for generating a spacing signal for transmission to said third means, wherein the clock control signal is provided to said clock in dependence upon the spacing signal, the clock stop signal, and the horizontal start signal.

7. A system as set forth in claim 6, wherein said third means comprises a clock controller circuit including:

a flip-flop having a clock input, operatively connected to said second means, for receiving the horizontal start signal, having a reset input connected to said video divider chain for receiving the clock stop signal, and having an output; and

a first OR gate, having a first input connected to the output of said flip-flop, having a second inverted input connected to said space control circuit and having an output connected to the clock.

8. A system as set forth in claim 7, further comprising means for generating first and second enable signals, wherein said space control circuit comprises:

a first one-shot multivibrator, operatively connected to said video divider chain and the computer, for generating a first space stop signal in dependence upon the first enable signal and the character repetition signal;

a second one-shot multivibrator, operatively connected to said video divider chain and the computer, for generating a second space stop signal in dependence upon the second enable signal and the character repetition signal; and

a second OR gate, having a first input connected to the first one shot multi-vibrator, having a second input connected to the output of said second one-shot multivibrator, and having an output connected to the second input of said first OR gate for providing either the first space stop signal or the second space stop signal as the spacing signal.

9. A system as set forth in claim 2, wherein said fifth means comprises a video insert keyer circuit, operatively connected to said first means and the computer, for generating the composite video signal and a stripped computer video signal, said system further comprising a summing amplifier, operatively connected to said sync separator circuit and to the video insert keyer circuit, for receiving the stripped computer video signal and the sync signal and for providing, as an output, a combined stripped computer video signal and sync signal.

10. A system as set forth in claim 9, wherein said video insert keyer circuit comprises:

means for providing a second half level reference signal;

a third comparator, operatively connected to the computer and to said means for providing the second half level reference signal, for generating the stripped computer video signal and the inverted stripped computer video signal;

means for providing a variable DC reference level signal;

a key switch circuit, operatively connected to said means for providing the variable DC reference level signal, the third comparator and said first means, for providing, as an output, one of the variable DC reference level signal and the NTSC video signal in dependence upon the stripped computer video signal and the inverted stripped computer video signal; and

a video distribution amplifier for receiving the output from the key switch circuit and for providing the output as the composite video signal.

11. A system, operatively connected to a computer for generating a computer video signal, for overlaying the computer video signal on an NTSC video signal, comprising:

first means for providing the NTSC video signal;

second means, operatively connected to said first means and the computer, for receiving the NTSC video signal and the computer video signal and for generating a vertical reset signal, a horizontal start signal and a composite video signal; and

third means, operatively connected to said second means and the computer, for receiving the vertical reset signal and the horizontal start signal and for generating control signals for controlling the rate at which the computer generates the computer video signal, so that the computer video signal is generated at the same rate as the NTSC video signal.

12. A system as set forth in claim 11, wherein said second means comprises:

a sync separator circuit, operatively connected to said first means, for receiving the NTSC video signal and for providing, as an output, a sync signal;

a vertical pulse processor circuit, operatively connected to said sync separator circuit and said third means, for receiving the sync signal and for generating the vertical reset signal; and

a horizontal pulse processor circuit, operatively connected to said sync separator circuit and said third means, for receiving the sync signal and for generating the horizontal start signal; and

a video insert keyer circuit, operatively connected to said first means and to the computer, for receiving the NTSC video signal and the computer video signal and for generating the composite video signal.

13. A system as set forth in claim 11 or 12, wherein said third means comprises:

a clock controller circuit, operatively connected to said second means, for receiving the horizontal start signal and for generating a clock control signal;

a clock, operatively connected to said clock controller circuit, for receiving the clock control signal and for generating a clock signal; and

a video divider chain, operatively connected to said second means, said clock controller circuit, said clock and the computer, for receiving the clock signal and the vertical reset signal, for providing a clock stop signal to said clock controller circuit and for providing the control signals to the computer.

14. A system as set forth in claim 13, wherein said video divider chain further generates a character repetition signal and wherein said third means further comprises a space control circuit, operatively connected between said video divider chain and said clock controller circuit, for receiving the character repetition signal and for generating a spacing signal for said clock controller circuit, wherein the clock control signal is provided to said clock by said clock controller circuit in dependence upon the horizontal start signal, the clock stop signal and the spacing signal.

15. A system as set forth in claim 14, wherein said clock controller circuit comprises:

a flip-flop having a clock input connected to said second means for receiving the horizontal start signal, having a reset input operatively connected to said video divider chain for receiving the clock stop signal, and having an output; and

a first OR gate having a first input connected to the output of said flip-flop, having a second input connected to said space control circuit for receiving the spacing signal and having an output connected to said clock.

16. A system as set forth in claim 15, wherein said video divider chain comprises:

a first counter, operatively connected to said clock and to said space control circuit, for receiving the clock signal and for generating the character repetition signal;

a second counter, operatively connected to said first counter and to the computer, for generating a first of the control signals;

a third counter, operatively connected to said second counter, the reset input of said flip-flop and the computer, for generating the clock stop signal and a second of the control signals; and

fourth, fifth and sixth counters, operatively connected to the third counter, said second means and the computer, for receiving the vertical reset signal and for generating a fourth, fifth and sixth of the control signals, respectively.

17. A system as set forth in claim 12, wherein said video insert keyer circuit also generates a stripped computer video signal and wherein said second means further comprises a summing amplifier, operatively connected to said video insert keyer circuit and to said sync separator circuit, for receiving the sync signal and the stripped computer video signal and for providing the combined computer video signal and sync signal.

18. A system as set forth in claim 12, further comprising an RF modulator, operatively connected to said video insert keyer circuit, for receiving the composite video signal and for generating an RF modulated composite video signal.

19. A system as set forth in claim 13, wherein said vertical pulse processor circuit comprises:

a ramp generator, operatively connected to said sync separator circuit, for generating a sawtooth signal;

means for providing a first three-forths level reference signal;

a first comparator, operatively connected to said means for providing the first three-forths level reference signal and to the ramp generator, for generating a vertical sync signal;

a first one-shot multivibrator, operatively connected to said first comparator, for generating a first monostable signal;

a second one-shot multivibrator, operatively connected to said first one-shot multivibrator, for generating a second monostable signal having a variable pulse width; and

a first differentiator, operatively connected to said second one-shot multivibrator and to said video divider chain, for generating the vertical reset signal.

20. A system as set forth in claim 19, wherein said horizontal pulse processor circuit comprises:

a third one-shot multivibrator, operatively connected to said sync separator circuit, for generating a third monostable signal;

a fourth one-shot multivibrator, operatively connected to said third one-shot multivibrator, for generating a fourth monostable signal having a variable pulse width; and

a second differentiator, operatively connected to said fourth one-shot multivibrator and to said clock controller circuit, for generating the horizontal start signal.

21. A system as set forth in claim 20, wherein said sync separator circuit comprises:

an amplifier, operatively connected to said first means, for amplifying the NTSC video signals;

means for providing a first half level reference signal; and

a second comparator, operatively connected to said amplifier and said means for providing the first half level reference signal, for generating the sync signal.