Buffer arrangement of a PCM exchange system

• US 4,429,386 A
• Filed: 01/05/1981
• Issued: 01/31/1984
• Est. Priority Date: 01/05/1981
• Status: Expired due to Term

• Current Assignee: Siemens Corp. (Siemens AG)
• Original Assignee: Siemens Corp. (Siemens AG)
• Inventors: Graden, Maynard
• Primary Examiner(s): Brigance, Gerald L.
• Application Number:
  US06/222,700
• Time in Patent Office: 1,121 Days
• Field of Search: 370/100, 370/103, 370/105, 370/108, 375/106, 375/107, 375/108, 375/118
• US Class Current: 370/517
• CPC Class Codes: H04J 3/0626 plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators

Abstract

A pulse code multiplex exchange system includes a buffer arrangement for compensating both short and long term phase drift of information between plesiochronous data paths each being controlled for block information transfer by a separate clock. An alignment buffer is arranged between the two data paths. It has two sections, each having a capacity for storing alternately one of two subsequent information blocks, and on chip address decoders for selecting write and read addresses. Separate address generators are associated with the buffer for generating consecutive write addresses under control of a first clock and read addresses under control of a second clock, respectively. A guard distance detector continuously monitors the distance between the present write address and the respective read address, and initiates a slip operation for switching subsequent read operations from one section of the alignment buffer to the other section, if the address distance falls short of a minimal guard distance.

Claims

1. A buffer arrangement of a pulse code multiplex exchange system for compensating both short and long term phase drift of information between a transmitting and a receiving data path, each data path being plesiochronously controlled by a first clock and a second clock, respectively, for transmitting of information blocks each composed of at least one pulse frame being, in turn, divided into a plurality of code words each representing a sample of a corresponding channel, said buffer arrangement comprising in combination:

(a) an alignment buffer connected between the first and the second data path and being composed of two sections, each having a capacity for storing alternately one of two subsequent information blocks in continuous storage locations;

(b) buffer addressing means associated with said alignment buffer for selecting write addresses and read addresses;

(c) address generating means connected to said buffer addressing means for generating consecutive write addresses for said alignment buffer under control of said first clock and for generating consecutive read addresses under control of said second clock;

(d) means for monitoring an offset between a current read address and the respective write address with respect to a predetermined minimal guard distance and for initiating a slip operation whenever said offset falls short of the guard distance, wherein said slip operation constitutes a read address jump from a storage location of one alignment buffer section to the corresponding storage location of the other alignment buffer section and this address jump is achieved by complementing the read address bit identifying a respective one of the alignment buffer sections; and

(e) means for solving access conflicts to said alignment buffer in case of simultaneous requests for read and write operations by granting the type of information requested first without completely suppressing a subsequent request for the other type of operation.

2. The buffer arrangement as recited in claim 1, wherein said address generating means include means for generating write and read request control signals, each provided in conjunction with a respective one of the write and read addresses;

and wherein said means for solving access conflicts comprise a contention logic unit having a clock input connected to receive a memory clock pulse train, a read control and write control inputs, each connected to receive a respective one of said request control signals, said contention logic unit further having a first control output for providing an enabling signal for initiating a memory operation and a second control output furnishing a signal for exclusively starting a write operation and further including a buffer logic network for buffering said read and write request control signals and for synchronizing enabling of requests with a read/write operation pattern determined by said memory clock pulse train.

3. The buffer arrangement as recited in claim 2, wherein the contention logic unit further comprises a toggle flipflop having an input connected to said clock input for receiving the memory clock pulse train and having two inverse outputs for supplying write cycle and read cycle control signals, respectively, and wherein said buffer logic network is composed of two identical network branches being symmetrically arranged with respect to said toggle flipflop, each network branch being designed for buffering a respective one of the read and write request control signals and including:

an inverter having an input and an output, and an AND-gate having first and second inputs and an output, said inverter input and said first AND-gate input being commonly connected to a respective one of said read/write control inputs; and

a first and a second JK flipflop each having a clock input connected to receive the memory clock pulse train, J and K data inputs, and set and reset outputs, said J data inputs of both JK flipflops being commonly connected to said AND-gate output, the K data input of the first JK flipflop being connected to said inverter output, and the K data input of second JK flipflop being connected to a respective one of the outputs of said toggle flipflop, said reset output of the first JK flipflop being connected to the second AND-gate input and the set input of said second JK flipflop providing a write and a read pulse, respectively, to be synchronized with the respective output signal of said toggle flipflop

4. The buffer arrangement as recited in claim 3, wherein said contention logic network further comprises:

two further AND-gates each being associated with a respective one of said network branches and having first and second inputs and an output, said first inputs of said further AND-gates each being connected to a respective one of said set outputs of the second JK flipflops, and the second inputs of said further AND-gates each being connected to a respective one of the outputs of said toggle flipflop; and

an OR-gate having two inputs and an output, said inputs of said OR-gate being connected to a respective one of said outputs of said further AND-gates, wherein said output of said OR-gate is connected to said first control output of said contention logic network and the output of the one of said further AND-gates associated with the network branch assigned for buffering write request control signals is connected to said second control output of the contention logic network.