Memory-based parallel data output controller
First Claim
1. A memory-based parallel data output controller for the extraction of predetermined bits from an inputted bit serial digital data stream for use with a frame synchronizer of the type having a word counter, a bit counter, a link synchronization status signal and a reference clock, said output controller receiving said inputted bit serial digital data stream and decommutating said predetermined extracted bits into multiple channels of predetermined parallel telemetry data to a plurality of peripheral devices, comprising:
- a first random access memory having address lines and at least as many memory address locations as there are channels, said word counter being connected to said address lines of said first random access memory which provides as its output an encoded peripheral device number and a first flag denoting either most significant bit or least significant bit first operation,a second random access memory having address lines and for outputting second and third flags to pick out the start and stop of said predetermined extracted bits, said encoded peripheral device number output from said first random access memory and said bit counter being connected to the address lines of said second random access memory,a serial-in parallel-out shift register for outputting said predetermined extracted bits in a parallel format representing said parallel telemetry data,shift register control means for receiving said bit serial digital data stream, said first, second and third flags, said link synchronization status signal and said reference clock and, therefrom, for developing and outputting a strobe pulse, a mode pulse, a shift pulse, and serial data pulse stream all of which output pulses being inputted into said shift register,decoding means connected to receive said encoded peripheral device number output from said first random access memory and receiving and being enabled by said output strobe pulse for selecting one of said plurality of peripheral devices to receive said parallel telemetry data from said shift register.
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Abstract
A memory-based parallel data output controller employs associative memories and memory mapping to decommutate multiple channels of telemetry data. The output controller contains a random access memory (RAM) (10) which has at least as many address locations as there are channels. A word counter addresses the RAM (10) which provides as its outputs an encoded peripheral device number and a MSB/LSB-first flag. The encoded device number and a bit counter address a second RAM (20) which contains START and STOP flags to pick out the required bits from the specified word number. The LSB/MSB, START and STOP flags, along with the serial input digital data go to a control block (30) which selectively fills a shift register (40,42) used to drive the parallel data output bus (32). A strobe pulse is also generated which enables a decoder (34) to select the appropriate peripheral device using the encoded device number. A microcomputer connected to an address bus (16) can be used to set the contents of the RAMs via multiplexers (14,24) during the initialization phase using the technique of memory mapping.
7 Citations
3 Claims
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1. A memory-based parallel data output controller for the extraction of predetermined bits from an inputted bit serial digital data stream for use with a frame synchronizer of the type having a word counter, a bit counter, a link synchronization status signal and a reference clock, said output controller receiving said inputted bit serial digital data stream and decommutating said predetermined extracted bits into multiple channels of predetermined parallel telemetry data to a plurality of peripheral devices, comprising:
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a first random access memory having address lines and at least as many memory address locations as there are channels, said word counter being connected to said address lines of said first random access memory which provides as its output an encoded peripheral device number and a first flag denoting either most significant bit or least significant bit first operation, a second random access memory having address lines and for outputting second and third flags to pick out the start and stop of said predetermined extracted bits, said encoded peripheral device number output from said first random access memory and said bit counter being connected to the address lines of said second random access memory, a serial-in parallel-out shift register for outputting said predetermined extracted bits in a parallel format representing said parallel telemetry data, shift register control means for receiving said bit serial digital data stream, said first, second and third flags, said link synchronization status signal and said reference clock and, therefrom, for developing and outputting a strobe pulse, a mode pulse, a shift pulse, and serial data pulse stream all of which output pulses being inputted into said shift register, decoding means connected to receive said encoded peripheral device number output from said first random access memory and receiving and being enabled by said output strobe pulse for selecting one of said plurality of peripheral devices to receive said parallel telemetry data from said shift register. - View Dependent Claims (2, 3)
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Specification