Microprocessor memory management and protection mechanism

• US 4,442,484 A
• Filed: 10/14/1980
• Issued: 04/10/1984
• Est. Priority Date: 10/14/1980
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Pollack, Frederick J., Klebanoff, Jack L., Childs, Robert H. E. Jr.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Fleming, Michael R.
• Application Number:
  US06/197,052
• Time in Patent Office: 1,274 Days
• Field of Search: 364/200, 364/900
• US Class Current: 711/163
• CPC Class Codes: G06F 12/1491 in a hierarchical protection system, e.g. privilege levels, memory rings
• CPC Class Codes: G06F 9/468 Specific access rights for resources, e.g. using capability register

Abstract

A memory management and protection mechanism in which access to protected entitites is controlled. The protected entities are represented by descriptors. Each protected entity is accessed via a selector which comprises an index integer assigned to the descriptor at the time of its creation. Tasks are active entities which may perform accesses and therefore are subject to control. A task has certain access rights. Each protected entity is assigned a specific privilege level. Each task within the system operates at one and only one privilege level at any instant in time. Protected entities which reside at a privilege level which is equal or less privileged than the current privilege level (CPL) of the task are generally accessible. The effective privilege level (EPL) of an access to a protected entity is defined as the numeric maximum of the CPL and the requested privilege level (RPL) present in the selector pointing to the memory segment to be accessed. An access is permitted if and only if the EPL is numerically less than or equal to the descriptor privilege level (DPL), assigned to the protected entity.

Claims

1. For use in a data processing system having a memory for storing information which is classified into various categories called objects of said system, and a central processing unit connected to said memory,

said central processing unit including a protection mechanism having levels of privilege, wherein said central processing unit has access to tables stored in said memory, said tables containing object descriptors, said object descriptors providing controlled access to real memory space in said memory by a task (processing path) executing on said central processing unit,

each of said object descriptors being typed and assigned a descriptor privilege level (DPL), such that access is allowed to some of said objects within said memory and access is denied to others of said objects within said memory, depending upon the descriptor privilege level assigned to said objects, the type assigned in the object descriptor, the type of operation requested in said executing task, and the current privilege level (CPL) of execution of said executing task,

said central processing unit comprising:

memory accessing means connected to said memory, said memory accessing means including memory address registering means for registering memory addresses for use by said memory in accessing said objects stored in said memory,

first means connected to said memory accessing means for registering first access information, said first access information providing first memory address information for locating said tables of object descriptors stored in said memory;

second means for registering a plurality of privilege levels, said privilege levels being assigned to a linearly ordered set of more privileged and lesser privileged levels;

third means for registering a task state segment, said task state segment including indicators which associated one or more of said tables of object descriptors with a task (processing path), said associated tables of object descriptors, in the aggregate, representing the entire set of objects in the address space of the task;

fourth means, connected to said second means, for registering a current privilege level (CPL) at any instant for a currently executing task, said current privilege level being a single unique member of said plurality of privilege levels registered in said second means, said CPL being based upon the progress of execution of said currently executing task;

fifth means for registering a segment selector, said segment selector including identifying means for uniquely identifying a particular object descriptor, said particular object descriptor being one of said object descriptors of said associated tables of object descriptors, within said address space of said task;

said fifth means including means for registering access rights information, said access rights information comprised of a number of bits of information, including descriptor privilege level bits (DPL) and type bits;

said type bits including bits for classification of said object descriptors into segment descriptors and control descriptors, said segment descriptors being permitted usage only for memory access and said control descriptors being permitted usage only for change of the operation path; and

,

logic means connected to said third, fourth, and fifth means, said logic means including comparing means connected to said fourth means and to said fifth means for comparing said CPL and said DPL of said particular object descriptor,

said logic means including output means, connected as an input to said first means, for permitting access to said particular object indicated by said selector (registered in said said fifth means), by use of said first memory address information, said access being permitted only upon the condition that said access is from a more privileged current privilege level (registered in said fourth means) to the same or a less privileged level as specified by the DPL (registered in said fifth means) of said particular object descriptor.

2. The combination in accordance with claim 1 wherein said fifth means includes:

sixth means for registering at least one of said object descriptors;

wherein said type bits in said descriptor include bits for indicating the representation of space in real memory; and

,

wherein an object descriptor classified by said type bits as a segment descriptor includes information indicating the lowest permitted address to be accessed (segment base) and the highest permitted address to be accessed (limit);

seventh means for registering a pointer, said pointer containing a segment selector and offset, said seventh means including means for calculating a real memory address of a real memory location by using said segment selector and offset and for placing said real memory address on an output of said seventh means;

eighth means connected to said output of said seventh means and to said sixth means for calculating whether said real memory address on said output of said seventh means is between said highest and lowest permitted real memory address registered in said sixth means; and

means included in said eighth means for signaling a fault upon the condition that said pointer registered in said seventh means is outside the permitted range indicated by said highest and lowest permitted real address registered in said sixth means.

3. The combination in accordance with claim 2 wherein said type bits registered in said fifth means include further bits for classifying at least one of said control descriptors as a procedure gate descriptor (as indicated by said further bits in said type), said procedure gate descriptor being a control descriptor and including a pointer indicating a target procedure;

ninth means for registering at least one of said procedure gate descriptors; and

,

violation detector means connected to said fifth means, to said memory accessing means, and to said ninth means,

said violation detector means including output means connected as an input to said first means for limiting usage of said procedure gate descriptor exclusively to a plurality of operations as indicated by the type bits of said procedure gate descriptor.

4. The combination in accordance with claim 1 or claim 2 wherein

said type bits includes further bits for classifying one of said segment descriptors (as indicated by said further bits in said type) as a task state segment descriptor,

said task state segment descriptor recording the existence of a task (processing path),

said real memory space represented by said task state segment descriptor indicating space in real memory for storage of information representing the status and address space of said task,

said real memory space representing a task state segment;

p1 said combination further comprising;

tenth means connected to said memory accessing means for registering second access information, said second access information providing second memory address information for locating a task state segment descriptor in said memory,

said task state segment descriptor including;

a number of bits specifying descriptor privilege level (DPL) and type bits,

information indicating the lowest permitted real memory address to be accessed (segment base) and the highest permitted real memory address to be accessed (limit),

and

means for indicating the gross status of the task as busy or not busy by means providing for dynamic modification of said type bits of said task state segment descriptor,

said task state segment including detailed information sufficient to resume the path of processing of said task when said task is not actively processing;

thirteenth means responsive to the registering of a selector, said selector pointing to one of said task state segment descriptors,

whereby the entire status of the processing path of the processor is recorded in the task state segment of said processing path and the processing path is diverted from the task registering said selector to a new processing path indicated by the contents of said task state segment indicated by said selector; and

fourteenth means for recording in said task state segment indicated by said selector a separate selector indicating the task state segment representing the immediately prior processing path.

5. The combination in accordance with claim 4 wherein said task state segment descriptor includes third access information providing third memory address information for locating a task state segment,

said task state segment including pointers to a plurality of stack segments, a separate stack segment being provided for each of said plurality of privilege levels.

6. The combination in accordance with Claim 5 wherein said procedure gate descriptor includes a number of parameters required by said target procedure indicated by said pointer;

tenth means for registering said number of parameters required by said target procedure;

eleventh means connected to said fifth means and to said ninth means, responsive to said segment selector and to said procedure gate descriptor for determining the act of transition to a more privileged level;

8. The combination in accordance with Claim 4 wherein said combination is for use with a primary processor which supports a plurality of subsidary processors, said primary processor including means for indicating the diversion of execution from one task to another task without requiring said task state segment to maintain the entire status of the processing task of said subsidary processors, the combination further comprising:

fifteenth means for recognizing the occurrence of a change in task of the primary processor from one of said tasks to another of said tasks;

sixteenth means connected to said fifteenth means for recording the occurrence of said change from one task to another task in a plurality of task switched (TS) bits, said task switched bits each being assigned to one of said plurality of subsidiary processors;

seventeeth means connected to said sixteenth means responsive to said task switched bits diverting said primary processor to a processing path suitable for changing the assignment of said subsidary processor from the previous task to the present task upon the condition that an attempt is made to utilize said subsidiary processor subsequent to said recording of change from one task to another.

9. The combination in accordance with claim 1 wherein:

said fifth means for registering a segment selector includes means for registering bits within said segment selector signifying a requested privilege level (RPL); and

wherein,

said comparing within said logic means further includes sixth means for comparing said CPL, RPL, and DPL, said sixth means connected to said output means of said logic means so as to permit access to said particular object by said selector only upon the condition that said DPL of said descriptor indicated by said selector is equal to or less than the privilege level of the lesser privileged of the privilege levels indicated by said RPL and said CPL.

10. The combination in accordance with claim 1 wherein said fifth means for registering a segment selector includes a plurality of segment registers, each segment register having an associated descriptor register for storing one of said object descriptors,

said segment registers including classification means for classifying said segment registers into two categories, the first of said categories indicating that a segment descriptor is for an executable segment and the second of said categories indicating that a segment descriptor is for a data segment.

11. The combination in accordance with claim 9 further comprising:

means connected to said segment descriptor registers for distinguishing said first category indicating that a segment is an executable segment;

said type bits including bits for indicating that said executable segment is nonconforming or conforming, depending upon the value of said type bits of said segment descriptor for an executable segment;

said comparing means within said logic means further including eighth means responsive to said DPL of said executable segment descriptor, said eighth means connected to said output means of said logic means so as to permit access to said particular object by said selector only upon the condition that said type bits indicate a nonconforming executable segment and the selector of said segment descriptor does not come from a procedure gate, and further including means operative upon the condition that said DPL of said segment descriptor is of different privilege than said CPL, for preventing the corresponding segment from being accessed; and

,

alternately, operative upon the condition that said type bits of said segment descriptor indicate a conforming executable segment, and further including means operative upon the condition that said DPL of said segment descriptor is of lesser privilege than said CPL, for preventing the corresponding segment from being accessed; and

alternately, operative upon the condition that said type bits of said segment descriptor indicate a conforming executable segment, and further including means operative upon the condition that said DPL of said segment descriptor is of greater privilege than said CPL, for preventing the corresponding segment from being accessed; and

,

said comparing means further including ninth means responsive to said type bits, said ninth means connected to said output means of said logic means so as to permit access to said particular object by said selector only upon the condition that said type bits indicate a nonconforming executable segment, said selector of said segment descriptor coming from a procedure gate when said DPL of said segment is of greater privilege than said CPL

and wherein, means are provided for changing said CPL to be equal to the DPL of said segment, and for changing the current stack segment to the stack segment assigned in said task state segment for the new CPL resulting in the invocation of a new stack segment at the new CPL, and for changing the RPL in said segment selector to be equal to said DPL; and

conversely, upon the condition that said type bits indicate an executable conforming segment, for changing said RPL bits in said selector to be equal to the original CPL.

12. The combination in accordance with claim 1 wherein said type bits include further bits for classifying at least one of said control descriptors as a task gate descriptor, said task gate descriptor including a selector to a task state segment descriptor;

the combination further comprising;

sixth means connected to said fifth means, for registering a task state segment descriptor,

said task gate descriptor including a number of bits specifying a descriptor privilege level (DPL), type bits and other information including a selector whose corresponding descriptor is of said task state segment descriptor type.

13. The combination in accordance with claim 3 or claim 11 wherein means are provided for connection to an external device and wherein one of said tables comprising said address space of said task is designated as an interrupt descriptor table (IDT) wherein is recorded all of the objects responsive to external signals (interrupts),

said IDT consisting of a plurality of descriptors of the type of said control descriptors, said control descriptors consisting of at least said type procedure gate and said type task gate;

tenth means responsive to the occurrence of an external signal from said external device for obtaining a number from said signalling external device representing an interrupt selector and for providing an interrupt operation signal,

said interrupt selector being a specialized selector within said task address space to be specialized to indicate a descriptor recorded in said IDT;

eleventh means connected to said tenth means and responsive to said interrupt operation signal for registering said interrupt selector within said IDT, said interrupt selector uniquely identifying one of the descriptors with said IDT;

twelfth means connected to said tenth and eleventh means for performing the operation indicated by the contents of said control descriptor, to thereby divert the operation of said task to the performance of the procedure or task indicated by the pointer or selector recorded within said object descriptor;

said twelfth means including means responsive to said procedure gate for diverting execution to the location indicated by said pointer in said procedure gate,

said twelfth means including means responsive to said task gate wherein the task previously operating has the previous task state recorded in the previously active task state segment, said task state segment indicated by said selector in said task gate being utilized as the source of the subsequent processing path state,

said twelfth means including means for recording within said new task state segment the selector to said previous task state segment descriptor.

7. twelfth means connected to said ninth means and to said eleventh means, responsive to said procedure gate descriptor for copying said number of parameters from the lesser privileged stack to the greater privilege stack;

and

thirteenth means for recording the previous location of the lesser privileged stack upon the greater privileged stack.