Electronic thermostat with repetitive operation cycle

• US 4,469,274 A
• Filed: 02/19/1982
• Issued: 09/04/1984
• Est. Priority Date: 05/27/1980
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Michael R. Levine
• Inventors: Levine, Michael R.
• Primary Examiner(s): Wayner, William E.
• Application Number:
  US06/350,522
• Time in Patent Office: 928 Days
• Field of Search: 236/46 R, 236/47, 165/12, 364/569, 364/557, 364/418, 364/505, 340/309.1
• US Class Current: 236/46.00R
• CPC Class Codes: F23N 5/203 using electronic means
• CPC Class Codes: G05D 23/1904 variable in time
• CPC Class Codes: G05D 23/24 the sensing element having a resistance varying with temperature, e.g. a thermistor

Abstract

An electronic multiple-setback thermostat for residential and commercial use includes an internal clock having a week-long cycle. The thermostat is programmed by the operator, usually manually actuable input devices, to control the furnace/air conditioning system to achieve a schedule of temperatures over the weekly period by simply inputting the temperature desired to be attained at the time of entry. Each temperature entry may be programmed to reoccur on a daily basis or to modify the program on a once-a-week basis. The thermostat employs an internal clock which controls memory addresses so that each memory location is representative of a short time period during the weekly cycle. A desired temperature signal is entered in a memory location determined by the clock state at the time of entry and is read out to the control system each time that time state reoccurs.The external temperature sensor employs a thermistor controlled oscillator that is used as the system clock source during failures of the primary power source.

Claims

1. An electronic controller comprising:

a clock operative to generate electrical signals representative of times within a repetitive time cycle and a repetitive subcycle which is a divisor of the cycle;

a memory;

input means, responsive to said clock, for entering set points into the memory;

means, controlled by the clock, for reading set points out of the memory;

means, controlled by the operator, for placing the system in a first mode wherein an inputted set point is stored in memory or in a second mode wherein a set point stored in the memory is recalled each time cycle; and

means, for controlling the input means before the clock reaches a predetermined state, to store an inputted set point in a plurality of memory locations for recall at the same time during each clock subcycle, and for controlling the input means to store an inputted set point in a single memory location, after the clock reachs said predetermined state, for recall once in a plurality of clock subcycles.

2. The system of claim 1 wherein said clock cycle is one week and the clock subcycle is one day.

3. The system of claim 1 in which said system has a third mode wherein the changes in said point are not entered into memory.

4. The system of claim 1 wherein the memory consists of a number of sections equal to the number of subcycles and a change in the set point is entered into each of the memory sections before the clock reaches said predetermined state.

5. A controller for a process, comprising:

a clock operative to generate signals representative of time within a repetitive time cycle in terms of a particular division of the time cycle and of the time within each division;

means for generating signals representative of a set point;

a memory; and

means for controlling the storage of set point signals in the memory in a first manner, in which a set point signal is recorded once for a clock cycle before the clock reaches a predetermined state, and in a second manner, in which a set point is recorded once for each division of the clock cycle, after the clock reaches said predetermined state.

6. The controller of claim 5 wherein said clock cycle consists of a week and a clock subcycle consists of a day.