Method of fabricating an MOS memory array having electrically-programmable and electrically-erasable storage devices incorporated therein

• US 4,490,900 A
• Filed: 01/29/1982
• Issued: 01/01/1985
• Est. Priority Date: 01/29/1982
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Seeq Technology, Inc. (Broadcom, Inc.)
• Inventors: Chiu, Te-Long
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/343,845
• Time in Patent Office: 1,068 Days
• Field of Search: 29/571, 29/576 B, 29/576 W, 29/578, 29/577 R, 29/571 C, 148/1.5, 148/187, 148/188, 427/93, 427/94, 357/22, 357/24, 357/41, 357/59
• US Class Current: 438/591
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for fabricating an MOS memory array is disclosed, wherein the method includes steps for constructing electrically-programmable and electrically-erasable memory cells (2, 198, 200) in combination with assorted peripheral devices (202, 204, 206) on a semiconductor substrate (8, 71). Tunneling regions (20, 78) are formed in the substrate (8, 71) and thin tunnel dielectrics (22, 84) comprised of silicon dioxide/oxynitride material are grown over the tunneling regions (20, 78) to facilitate transport of charge carriers between the tunneling regions (20, 78) and subsequently-fashioned floating gate structures (14R, 14L, 156) in the memory cells (2, 198, 200). A first layer of doped polycrystalline silicon is then deposited over the substrate and etched to define large polysilicon areas. An oxide layer is grown over the large polysilicon areas in a manner such that out-diffusion of the impurity present in the large polysilicon areas is prevented. Thereafter, a second layer of doped polycrystalline silicon is deposited over the substrate and etched together with the large polysilicon areas to define the memory cell floating gate structures (14 R, 14L, 156) as well as various memory cell program and control gates (16R, 16L, 40R, 40L, 128, 132) and peripheral device control gates (136, 138). Source and drain regions (34, 36, 58, 60, 64, 66, 168-179) for the memory cells (2, 198, 200) and the peripheral devices (202, 204, 206) are established by implanting an impurity in the semiconductor substrate (8, 71), using the memory cell program and control gates (16R, 16L, 40R, 40L, 128, 132) and the peripheral device control gates (136, 138) for alignment. Protective coverings of refill oxide (188) and VapOx (190) are formed over the substrate to complete the fabrication process.

Claims

1. A method of constructing a tunnel dielectric for an MOS device such that charge carriers supplied by an active region in the device can be transported through said tunnel dielectric, said method comprising the steps of:

forming an oxide layer over the active region to provide said tunnel dielectric; and

converting at least a portion of said oxide layer to an oxynitride material, said oxynitride material exhibiting a relatively low potential barrier to charge carriers tunnelling therethrough.

2. The method as set forth in claim 1, wherein said step of converting at least a portion of said oxide layer to said oxynitride material includes the further step of annealing said oxide layer in an ammonia-containing gas.

3. A method as set forth in claim 2, wherein said step of annealing said oxide layer in an ammonia-containing gas is carried out at a temperature between 900°

C. and 1200°

C.

4. A method as set forth in claim 1, wherein the active region of the device is formed in the device substrate and said step of forming an oxide layer over the active region includes the step of thermally growing said oxide layer on the surface of the device substrate.

5. A method as set forth in claim 4, wherein the device substrate is comprised of silicon and said oxide layer is comprised of silicon dioxide.

6. A method as set forth in claim 5, wherein said oxynitride material is comprised of silicon oxynitride.

7. A method as set forth in claim 1, wherein said oxide layer has a thickness between 50 A and 150 A.

8. A method as set forth in claim 1 including the further step of forming an additional layer of oxynitride material over said oxide layer following said step of converting at least a portion of said oxide layer to said oxynitride material.

9. A method as set forth in claim 1, including the further step of depositing a layer of electrically-conductive material over said oxide layer following said step of converting at least a portion of said oxide layer to said oxynitride material.

10. A method of forming an interpoly oxide layer of predetermined thickness on a first semiconductor gate in an MOS device fabricated on a substrate such that said interpoly oxide layer exhibits high breakdown voltages, low surface charge states and low mobile ion contamination, said method comprising the steps of:

thermally growing an oxide layer over the first semiconductor gate in an atmosphere containing oxygen and gaseous hydrochloride at a temperature of approximately 800°

C. until the thickness of said oxide layer reaches approximately 100 A.; and

continuing to grow said oxide layer in an atmosphere containing oxygen and gaseous hydrochloride at a temperature of at least approximately 1,000°

C. until said oxide layer reaches the predetermined thickness.

11. A method as set forth in claim 10 wherein said first semiconductor gate is fabricated from a layer of doped polycrystalline silicon, said method comprising the further step of depositing a second layer of doped polycrystalline silicon on said oxide layer to form a second semiconductor gate after said oxide layer has reached the predetermined thickness.