Bidirectionally source stacked FETs with drain-referenced common gating

• US 4,491,750 A
• Filed: 09/28/1982
• Issued: 01/01/1985
• Est. Priority Date: 09/28/1982
• Status: Expired due to Fees

• Current Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Original Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Inventors: Janutka, William J.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Bertelson, David R.
• Application Number:
  US06/425,158
• Time in Patent Office: 826 Days
• Field of Search: 307/241, 307/242, 307/570, 307/571, 307/572, 307/577, 307/582, 307/583, 307/584, 307/270, 307/304, 307/200 B, 307/499, 307/501, 307/352, 307/353, 307/579, 307/585, 357/23 GP, 330/269
• US Class Current: 327/436
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/6874 in a symmetrical configuration

Abstract

A bidirectionally source stacked FET circuit is provided with drain-referencing of the gating circuitry, instead of source-referencing. This requisite gate to source potential to charge the gate and effect conduction of the FETs is provided by referencing the gate circuitry to a common anode point of diodes having their cathodes connected to the drains of the FETs. The common anode point is at substantially the same potential as the common source point of the FETs. The gate charging potential is provided by current from a current source through a resistor to the common anode point, which IR drop establishes the requisite gate voltage to drive the corresponding FET into conduction regardless of the polarity of first and second main terminals at respective FET drains.

Claims

1. A bidirectional FET circuit comprising:

first and second enhancement mode power FETS of like channel type connected source to source in series relation between main power terminals connectable in circuit with a load and a source of potential, current conduction in one direction flowing through the series connection of the drain-source current path of said first FET and the forward biased substrate-drain PN junction of said second FET, and in the opposite direction through the series connection of the drain-source current path of said second FET and the forward biased substrate-drain PN junction of said first FET;

current source means connected to the gates of said power FETs; and

resistance means connected from a point common between the gates of said power FETs and to each of the drains of said power FETs.

2. A bidirectional FET circuit comprising:

first and second enhancement mode power FETs connected source to source in series relation between main power terminals connectable in circuit with a load and a source of potential, current conduction in one direction flowing through the series connection of the drain-source current path of said first FET and the forward biased substrate-drain PN junction of said second FET, and in the opposite direction through the series connection of the drain-source current path of said second FET and the forward biased substrate-drain PN junction of said first FET;

current source means connected to the gates of said power FETs; and

resistance means connected from a point common between the gates of said power FETs and to each of the drains of said power FETs, and wherein said resistance means comprises;

a first diode connected at one end to the drain of said first power FET;

a second diode connected at one end to the drain of said second power FET; and

a resistor connected at one end to said common gate point, and connected at the other end to a point common to the other ends of said diodes.

3. A bidirectional FET circuit comprising:

a plurality of pairs of enhancement mode power FETs, each pair comprising first and second FETs connected source to source in series relation, said pairs connected in series between first and second main power terminals, current conduction in one direction flowing through the series connection of the drain-source current path of said first FET and the forward biased substrate-drain PN junction of said second FET, and in the opposite direction through the series connection of the drain-source current path of said second FET and the forward biased substrate-drain PN junction of said first FET;

current source means connected between a gate terminal and the gates of each said power FET pair; and

a plurality of resistance means, one for each said power FET pair, each resistance means connected from a point common between the gates of its respective said power FET pair to each of the drains of its respective said power FET pair.

4. The invention according to claim 3 wherein each said resistance means comprises:

a first diode connected at one end to the drain of the first FET of its respective said power FET pair;

a second diode connected at one end to the drain of the second FET of said respective said power FET pair; and

a resistor connected at one end to said common gate point, and connected at the other end to a point common to the other ends of said diodes.

5. The invention according to claim 4 wherein said current source means comprises a source follower mode FET having a gate connected to the same potential level as one of said main terminals.

6. A three terminal bidirectional FET circuit comprising:

a plurality of pairs of enhancement mode power FETs, each pair comprising first and second FETs connected source to source in series relation, said pairs connected in series between first and second main power terminals, current conduction in one direction flowing through the series connection of the drain-source current path of said first FET and the forward biased substrate-drain PN junction of said second FET, and in the opposite direction through the series connection of the drain-source current path of said second FET and the forward biased subsrate-drain PN junction of said first FET;

a plurality of pairs of diodes, one pair of diodes for each said power FET pair, each diode pair comprising first and second diodes having common anodes, the first diode having a cathode connected to the drain of the first power FET of its respective said pair, the second diode having a cathode connected to the drain of the second power FET of its respective said pair; and

current source means connected to said gates of said power FETs of each said pair for driving said power FETs into conduction, said anodes of each pair of said diodes being coupled to said current source means.

7. The invention according to claim 6 comprising a plurality of resistors having one end connected to said current source means and another end connected to said common anode point of a respective said pair of diodes.

8. The invention according to claim 7 comprising a plurality of decoupling diodes each connected between said current source means and a respective said resistor, and also connected between said current source means and respective said gates of respective said power FET pairs.