Voltage transient protection circuit

• US 4,495,536 A
• Filed: 12/27/1982
• Issued: 01/22/1985
• Est. Priority Date: 12/27/1982
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Bynum, Byron G.
• Primary Examiner(s): Moose, Jr., Harry E.
• Application Number:
  US06/453,402
• Time in Patent Office: 757 Days
• Field of Search: 361/18, 361/91, 361/93, 361/98, 361/103, 361/101, 361/110, 361/111, 323/277, 323/276, 323/275, 323/292, 323/312
• US Class Current: 361/58
• CPC Class Codes: H02H 7/20 for electronic equipment for converters H02H7/10; for electric measuring instruments G01R1/36; for dc voltage or current semiconductor regulators G05F1/569; for amplifiers H03F1/52; for electronic switching circuits H03K17/08

Abstract

A three terminal integrated low-resistant series switch circuit which buffers load electronics from extreme input voltage conditions. The circuit comprises a series pass transistor the conductivity of which is controlled by control circuitry in cooperation with feedback control. In response to the input exceeding a predetermined operating potential the series pass transistor is driven toward saturation and is maintained in this state by feedback whereby only that load current required by the load electronics is supplied for increased efficiency. The control circuitry is responsive to the signal at the input thereof exceeding a predetermined level for rendering the series pass transistor nonconducting to protect the load electronics from extreme voltage excursions. A feature of the circuit is that the epitaxial layer within which the control circuit is formed is operated at a lower voltage than that of the substrate.

Claims

1. A monolithic integrated protection circuit for providing protection to a load coupled thereto, comprising:

a series-pass transistor having first and second main electrodes coupled between an input and an output of the protection circuit and a control electrode;

control circuit means coupled to said control electrode of said series-pass transistor which is responsive to an external signal applied to an input thereof exceeding a threshold value for rendering said series-pass transistor conductive; and

feedback circuit means responsive to said series-pass transistor being driven into saturation for providing a feedback control signal to said control circuit means to cause said series-pass transistor to supply the required load current to said output of the protection circuit while minimizing current drive to said control electrode.

2. The protection circuit of claim 1 including protection circuit means responsive to the voltage appearing at said input of the protection circuit exceeding a predetermined value for causing said control circuit means to render said series-pass transistor nonconducting.

3. The protection circuit of claim 1 or 2 including thermal control circuit means responsive to the ambient temperature of the integrated circuit exceeding a predetermined temperature for causing said control circuit means to render said series-pass transistor nonconducting.

4. The circuit of claim 3 including short-circuit protection means responsive to said load current exceeding a threshold value for causing said control circuit means to limit said load current at substantially said threshold value.

5. The circuit of claim 4 wherein said control circuit means includes a first field effect transistor (FET) having a gate electrode and source and drain electrode, said source and drain electrodes being connected in series with said control electrode of said series-pass transistor, said gate being coupled to a control input of said control circuit means.

6. The circuit of claim 5 wherein said control circuit means includes:

a first transistor having an emitter, a base and multi-collectors, said emitter being coupled to said input of the protection circuit;

latch circuit means coupled between said base and a first collector of said first transistor for regulating the current flow through said first collector to a predetermined value; and

first circuit means coupling a second collector of said first transistor with the gate of said first FET such that said first FET is rendered conductive as said first transistor is rendered conductive.

7. The circuit of claim 6 wherein said control circuit means includes a second FET having a source-drain path connected between said gate of said first FET and a common terminal, and a gate connected to said control input, and resistive divider means connected between said control input and said common terminal.

8. The circuit of claim 6 wherein said feedback circuit means comprises a region of semiconductor material of like conductivity type as said second main electrode of said series-pass transistor formed in said epitaxial layer in proximity to said series-pass transistor, said region being coupled to said control input of said control circuit means.

9. The circuit of claim 6 wherein said protection circuit includes:

a second transistor having an emitter coupled to said input of the protection circuit, and a base and collector interconnected at a first common node; and

Zener diode means coupled between said common node and said control input terminal of said control circuit means.

10. The circuit of claim 9 wherein said second transistor includes a second collector connected to said control electrode said series-pass transistor.

11. The circuit of claim 7 wherein said latch circuit means includes:

a third FET having a gate, the source-drain path thereof being coupled in series between said base of said first transistor and a common node;

a fourth FET having a gate coupled to said common node and a source-drain path coupled between said gate of said third FET and said common terminal;

second circuit means connecting said gate of said third FET to said first collector of said first transistor; and

third circuit means coupled between said common node and said common terminal.

12. A monolithic integrated circuit having an input and an output, comprising:

a vertical structured PNP transistor having an emitter and collector coupled respectively to the input and output of the circuit and a base, said collector being formed by a portion of the substrate comprising the integrated circuit, said base being formed by a region of the epitaxial layer of the integrated circuit and said emitter being formed in a region of said epitaxial layer;

control circuit means formed in said epitaxial layer which is responsive to an external signal applied to the input of the integrated circuit for controlling the conduction of said PNP transistor wherein said PNP transistor tends to be driven into saturation; and

sense circuit means for sensing when said PNP transistor is driven into saturation for providing a feedback control signal to an input of said control circuit means to minimize the base current drive of said PNP transistor with respect to the collector current whereby said substrate is maintained at a more positive potential than said epitaxial layer.

13. The circuit of claim 12 including protection circuit means coupled between the input of the circuit and said input of said control circuit means for providing a control signal thereto in response to said external signal exceeding a predetermined value such that said PNP transistor is rendered nonconductive.

14. The circuit of claim 13 including short circuit protection means coupled to said input of said control circuit means which is responsive to said collector current of said PNP transistor exceeding a predetermined value for providing a control signal to said control circuit means to regulate said collector current at substantially said predetermined value.

15. The circuit of claim 13 or 14 wherein said sense circuit means comprises a region of semiconductor material of like conductivity as said emitter region of said PNP transistor in close proximity to said PNP transistor.

16. The circuit of claim 15 wherein said control circuit means:

includes a first field effect transistor (FET) having a gate, source and drain electrodes, said source-drain electrodes being coupled in series between said base of said PNP transistor and a common terminal of the circuit;

a first transistor of like conductivity type as said PNP transistor having an emitter coupled to the input of the circuit, a base, first and second collectors;

latch circuit means coupled between said base and first collector of said first transistor to said common terminal for regulating the collector current sourced from said first collector; and

first circuit means for coupling said second collector of said first transistor with said gate of said first FET.

17. The circuit of claim 16 wherein said control circuit means further includes a second FET having a source-to-drain path coupled in series between said gate of said first FET and said common terminal, the gate thereof being coupled to said input of said control circuit means.

18. The circuit of claim 17 wherein said protection circuit means includes:

a second transistor having an emitter coupled to the input of the circuit, a base and a collector, said base and collector being interconnected; and

Zener diode means coupled between said interconnected base and collector of said second transistor and said input of said control circuit means.

19. The circuit of claim 18 wherein said short circuit protection means comprises a second collector region of said PNP transistor formed in lateral spaced relationship to said emitter and base of said PNP transistor, said second collector region being coupled to said input of said control circuit means.

20. The circuit of claim 19 wherein said latch circuit means includes:

a third FET having a gate and a source-drain path coupled in series between said base of said first transistor and a common node;

a fourth FET having a gate coupled to said first common node and a source-drain path coupled in series between said base of said first transistor and a common node;

a fourth FET having a gate coupled to said first common node and a source-drain path coupled between said gate of said third FET and said common terminal.

21. The circuit of claim 20 wherein said second transistor of said protection circuit includes a second collector coupled to said base of said PNP transistor.