Method for manufacturing three-dimensional semiconductor device by sequential beam epitaxy

• US 4,498,226 A
• Filed: 08/27/1982
• Issued: 02/12/1985
• Est. Priority Date: 08/31/1981
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha 72 Horikawa-Cho Saiwai-Ku Kawasaki-Shi Japan
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Inventors: Shibata, Kenji, Inoue, Tomoyasu
• Primary Examiner(s): Roy, Upendra
• Application Number:
  US06/412,241
• Time in Patent Office: 900 Days
• Field of Search: 29/576 B, 29/571, 148/1.5, 148/187, 357/23 VT, 357/91
• US Class Current: 438/152
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02598 monocrystalline
• CPC Class Codes: H01L 21/02675 using laser beams
• CPC Class Codes: H01L 21/02689 using particle beams
• CPC Class Codes: H01L 21/02691 Scanning of a beam
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for manufacturing a three-dimensional semiconductor device which is capable of preventing the stepwise disconnection of an interconnection layer and performing a high integration thereby and which comprises the steps of: forming a polycrystalline or amorphous semiconductor layer on an insulating film having an opening at a predetermined position of a first element covered on a single-crystalline semiconductor substrate having the first element; irradiating an energy beam to said semiconductor layer to grow a single crystal in a predetermined region in said semiconductor layer using as a seed crystal that part of the semiconductor substrate which contacts with semiconductor layer; and forming a second element on the grown single-crystalline semiconductor region and forming an interconnection between the first and second elements by using a part of the single-crystalline semiconductor region from said semiconductor substrate to said second element.

Claims

1. A method for manufacturing a three-dimensional semiconductor device comprising the steps of:

forming first and second semiconductor elements on the surface of a single-crystalline semiconductor substrate;

forming a first insulating film on said substrate;

forming a first opening in said first insulating film at a predetermined portion of said first semiconductor element;

forming a first polycrystalline or amorphous semiconductor layer on said first insulating film having said first opening;

irradiating said first semiconductor layer with an energy beam to grow a single crystal in a predetermined region in said first semiconductor layer using as a seed crystal that part of said semiconductor substrate which contacts said first semiconductor layer and to form a first single-crystalline semiconductor region;

forming at least a part of a third semiconductor element in said first single-crystalline semiconductor region;

forming an interconnection between said first and third semiconductor elements by using a part of said first single-crystalline semiconductor region from said semiconductor substrate to said third element;

forming a second insulating film having a second opening at a predetermined portion of said second semiconductor element so as to elongate on said first single-crystalline semiconductor region;

forming a second polycrystalline or amorphous semiconductor layer on said second insulating film having said second opening;

irradiating said second semiconductor layer with an energy beam to grow a single crystal at a predetermined region in said second semiconductor layer using as a seed crystal that part of said semiconductor substrate which contacts with the second semiconductor layer and to form a second single-crystalline semiconductor region; and

forming a remaining part of said third semiconductor element and forming an interconnection between said second and third semiconductor elements by using a part of said second single-crystalline semiconductor region from said semiconductor substrate to said third semiconductor element.

2. The method according to claim 1, further comprising the step of:

selecting said energy beam from the group consisting of an electron beam, a laser beam and ion beam.

3. The method according to claim 1, further comprising the step of:

selecting as said semiconductor element a MOS transistor.

4. The method according to claim 1, further comprising the step of:

selecting as said semiconductor element a MOSFET.

5. The method according to claim 1, further comprising the step of:

selecting said insulating film from the group consisting of an SiO₂, an SiN, an Al₂ O₃ and an SiN-SiO₂ two layer structure.

6. The method according to claim 1, further comprising the step of:

doping an impurity in said single-crystalline semiconductor region so as to form said interconnection.

7. The method according to claim 1, further comprising the step of:

selecting as said third semiconductor element a MOS transistor,

connecting a gate electrode to said first semiconductor element via said first single-crystalline semiconductor region.

8. The method according to claim 1, further comprising the step of:

selecting as said third semiconductor element a MOS transistor;

connecting a gate electrode to said second semiconductor element via said second single-crystalline semiconductor region.