Interface control system for high speed processing based on comparison of sampled data values to expected values

• US 4,516,202 A
• Filed: 07/30/1981
• Issued: 05/07/1985
• Est. Priority Date: 07/31/1980
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kadowaki, Yoshihiko
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Lee, Jameson
• Application Number:
  US06/288,498
• Time in Patent Office: 1,377 Days
• Field of Search: 364/200, 364/900, 364/492, 364/494, 364/400, 364/130, 364/140, 290/40 R, 340/892.5
• US Class Current: 714/49
• CPC Class Codes: G06F 13/122 where hardware performs an I/O function other than control of data transfer
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4226 with asynchronous protocol

Abstract

An interface control system between a plurality of devices, such as a channel and an I/O device, includes sampling means for high speed sampling input control signals on an interface, a compare circuit for comparing a current sampled value sampled by the sampling means with an expected value for the input control signal previously prepared in the system and with a previously sampled value, respectively, to produce a compare equal signal when the sampled value is equal to the expected value, a matrix logic circuit responsive to the compare equal signal to set an output signal line corresponding to the expected value and an expected value for next sampling, and a circuit to produce a signal indicating an error condition or an exceptional condition when the sampled value is not equal to the expected value and the previous sampled value, to activate another logic circuit.

Claims

1. An interface control system comprising:

(a) means coupled to an interface for sampling an input control signal at said interface;

(b) first compare means connected to said sampling means for comparing a current sampled value of said input control signal sampled by said sampling means with an expected value for the input control signal;

(c) response means connected to said first compare means for generating a response signal in response to said input control signal and a next expected value signal representing the expected value of the next input control signal in accordance with a predetermined interface operation specification when said first compare means indicates an equality between the current sampled value and the expected value; and

(d) means connected to said sampling means for storing a sampled value to provide a previously sampled value signal, second compare means connected to said sampling means and said storing means for comparing the current sampled value of said input control signal with said previously sampled value signal, and means connected to said first and second compare means for generating an abnormal condition signal when both of said first and second compare means indicate compare unequal conditions.

2. An interface control system according to claim 1, further comprising means for generating a mask signal to prevent response by said first and second compare means to an input control signal which may be neglected, and mask indicating means connected to said first and second compare means and responsive to said mask signal from said mask signal generating means for masking an input control signal which may be neglected when the current sampled value is compared with the previously sampled value by said second compare means or when the current sampled value is compared with the expected value by said first compare means to cause said first or second compare means to neglect the masked input control signal.

3. An interface control system between a channel and an input/output (I/O) device comprising;

microprogram control means connected to a basic processing unit to carry out start and termination operations of a command and connected to a main storage to control data transfer between said main storage and said channel; and

an I/O interface control circuit connected between said microprogram control means and said channel and operating under the control of control signals from said microprogram control means, said I/O interface control circuit including;

(a) sampling means coupled to an interface for sampling an input tag signal at said interface;

(b) first compare means connected to said sampling means for comparing a current sampled value of said input tag signal sampled by said sampling means with a previously generated expected value for the input tag signal and for producing a compare equal or a compare unequal signal as a result of said comparison;

(c) means connected to said sampling means for storing a sampled value to provide a previously sampled value signal;

(d) second compare means connected to said sampling means and for storing means for comparing the current sampled value of said input tag signal with said previously sampled value signal and for producing a compare equal or a compare unequal signal as a result of said comparison; and

(e) logic means connected to said first and second compare means responsive to a compare unequal signal from said second compare means and a compare equal signal from said first compare means to produce at least a response signal in response to said input tag signal of expected value and an expected value for the next sampling of said input tag signal.

4. An interface control system according to claim 3 further comprising AND means for ANDing the compare unequal signal from said second compare means with the compare equal signal from said first compare means, an output signal from said AND means being sent to said microprogram control means as a signal indicating an error condition or an exceptional condition of the input tag signal.

5. An interface control system according to claim 3 or 4 wherein said sampling means is program-controlled by said microprogram control means.

6. An interface control system according to claim 3 or 6 further comprising means for generating a mask signal to prevent response by said first and second compare means to an input tag signal which may be neglected, and mask register means connected to said first and second compare means and responsive to said mask signal from said mask signal generating means for generating an indication signal for masking an input tag signal which is not to be compared and for applying said indicating signal to said first and second compare means to inhibit operation thereof.

7. An interface control system according to claim 3 or 4 wherein said sampling means includes new input tag register means for storing the sampled input tag signal and said storing means includes an old input tag register means for storing the previously sampled value, and further comprising input tag expected value register means connected to said logic means for storing the expected value for the next sampled input tag value, means for applying the output of said new input tag register means to first input terminals of said second and first compare means, and means for applying the output of said old input tag register means and the output of said input tag expected value register means to second input terminals of said second and first compare means, respectively, the output of said second compare means being connected to said logic means whereby, when said second compare means produces a compare equal signal, said logic means is activated.

8. An interface control system according to claim 7 wherein said logic means includes a matrix logic circuit responsive to activation by the output of said second compare means for applying a predetermined signal value on an output tag line of said channel interface, generating said expected value for the next sampled input tag signal, generating a sequence updating signal and transferring the content of said new input tag register means to said old input tag register means.

9. An interface control system according to claim 3 further comprising data transfer control means coupled between said interface control circuit and said microprogram control means and responsive to an output of said logic means for controlling high speed data transfer between said channel and said I/O device.

10. An interface control system between a plurality of devices comprising:

(a) sampling means coupled to an interface for sequentially sampling input control signals on said interface;

(b) compare means connected to said sampling means for comparing a current sampled value of said input control signals sampled by said sampling means with an expected value for the input control signal which has previously generated and which varies with the input control signal and for comparing said current sampled value with the previously sampled value of the input control signal, to produce a compare equal signal or a compare unequal signal for each comparison operation;

(c) logic means connected to said compare means and responsive to the compare equal signal from said compare means for the comparison of the current sampled value and the expected value to produce a response signal in response to the input control signal of expected value and to generate an expected value for next sampling of the input control signal; and

(d) error detection means connected to said compare means and responsive to the compare unequal signals from said compare means for the comparison of the current sampled value and the expected value and the comparison of the current sampled value and the previously sampled value to produce a signal indicating an error condition or an exceptional condition of the input control signal.

11. An input/output interface controlling device for information exchange between a plurality of devices, such as a channel and one or more input/output devices, comprising:

sampling means connected to an interface for sampling an input signal from said interface;

first compare means connected to said sampling means for comparing a current sampled value of said input signal sampled by said sampling means with a previously generated expected value for the input signal to detect an equality between the sampled value and the expected value when the sampled value is equal to the expected value;

second compare means connected to said sampling means for comparing said current sampled value of said input signal with a previously sampled value to detect an unequality between the current sampled value and the previously sampled value, when the current sampled value is not equal to the previously sampled value, indicating that a change has occurred in said input signal; and

response circuit means connected to said first and second compare means and responsive to detection of an equality at said first compare means and detection of an inequality at said second compare means for producing a response signal to be applied to said interface and an expected value signal representing the expected value for the next input signal in accordance with a predetermined interface operation specification.

12. An input/output interface controlling device according to claim 11, further comprising gate circuit means connected to said first and second compare means for producing a signal indicating an error condition or an exceptional condition when the current sampled value is found to be not equal to the expected value and the previously sampled value of said input signal.

13. An input/output interface controlling device according to claims 11 or 12, further comprising an expected value register, connected between said first compare means and said response circuit means for temporarily storing said expected value signal which is generated by said response circuit means.

14. An input/output interface controlling device according to claims 11 or 12, further comprising means for generating a mask signal to prevent response by at least said first compare means to an input signal which may be neglected, and mask indicating means connected to said first compare means and responsive to said mask signal from said mask signal generating means for masking an input signal which is supplied to said first compare means when the current sampled value is not to be compared with an expected value from said response circuit means by the first compare means.

15. An input/output interface controlling device, according to claim 12, wherein said gate circuit means includes AND means for ANDing the compare unequal signal from said second compare means and the compare unequal signal from said first compare means to produce the signal indicating an error condition or an exceptional condition.

16. An input/output interface controlling device according to claim 13, further comprising new input tag register means connected to said sampling means for storing the current sampled value of said input signal and old input tag register means connected to said new input tag register means for storing the previously sampled value of said input signal, the output of said new input tag register means being connected to first input terminals of the first and second compare means and the output of said old input tag register means and the output of said expected value register being connected to second input terminals of said first and second compare means, respectively;

and means responsive to said first compare means producing a compare equal signal for activating said response circuit means.

17. An input/output interface controlling device according to claim 16, wherein said response circuit means includes means, when activated, for generating a sequence updating signal, for transferring the contents of said new input tag register means to said old input tag register means and for generating a signal to initiate the next sampling operation.

18. Input/output interface controlling device according to claim 11, wherein said response circuit means includes an alterable memory element for effecting operations in accordance with said predetermined interface operation specification.

19. An input/output interface controlling device for information exchange between a plurality of devices, such as a channel and one or more input/output devices, comprising:

sampling means connected to an interface for sampling an input signal from said interface;

first compare means connected to said sampling means for comparing a current sampled value of said input signal sampled by said sampling means with a previously generated expected value for the input signal to produce a compare equal signal when the sampled value is equal to the expected value;

second compare means connected to said sampling means for comparing said current sampled value of said input signal with a previously sampled value to produce a compare unequal signal, when the current sampled value is not equal to the previously sampled value, indicating that a change has occurred in said input signal; and

response circuit means connected to said first and second compare means and responsive to a compare equal signal from said first compare means and a compare unequal signal from said second compare means to produce a response signal to said interface and an expected value signal representing the expected value for the next input signal in accordance with a predetermined interface operation specification.