Method of making EPROM cell with reduced programming voltage

  • US 4,519,849 A
  • Filed: 07/22/1983
  • Issued: 05/28/1985
  • Est. Priority Date: 10/14/1980
  • Status: Expired due to Term
First Claim
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1. In the fabrication of an MOS electrically programmable read-only memory cell wherein a layer of polysilicon is formed insulated from a substrate, said layer being used to define a floating gate member for said cell, an improvement comprising the steps of:

  • forming an oxide layer of a predetermined thickness over said polysilicon layer;

    forming a silicon nitride layer over said oxide layer;

    etching said silicon nitride layer, oxide layer and polysilicon layer so as to define a dimension of said floating gate member;

    subjecting said substrate to an elevated temperature so as to grow an oxide region at edges of said floating gate member such that a thicker oxide develops at said edges of said floating gate member when compared to said oxide layer at the central portion of said floating gate member;

    whereby said edges of said floating gate are protected by a thicker oxide region thereby reducing undesirable loss of charge from said floating gate member to overlying structures.

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