Method of making EPROM cell with reduced programming voltage

• US 4,519,849 A
• Filed: 07/22/1983
• Issued: 05/28/1985
• Est. Priority Date: 10/14/1980
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Korsh, George J., Holler, Mark A., Perlegos, George, Gargini, Paolo
• Primary Examiner(s): Roy, Upendra
• Application Number:
  US06/515,990
• Time in Patent Office: 676 Days
• Field of Search: 29/571, 29/576 B, 148/1.5, 148/187, 357/91
• US Class Current: 438/453
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel

Abstract

An improved floating gate MOS EPROM cell which is programmable at a lower potential (12 volts) than prior art devices which often require 25 volts. The oxide thickness between the floating gate and overlying control gate is thicker at the edges of the floating gate than in the central portion. The thicker oxide at the edges prevents uncontrolled DC erasing. This allows a thinner oxide to be used in the central portion and provides the increased capacitance coupling needed for programming at a lower potential.

Claims

1. In the fabrication of an MOS electrically programmable read-only memory cell wherein a layer of polysilicon is formed insulated from a substrate, said layer being used to define a floating gate member for said cell, an improvement comprising the steps of:

forming an oxide layer of a predetermined thickness over said polysilicon layer;

forming a silicon nitride layer over said oxide layer;

etching said silicon nitride layer, oxide layer and polysilicon layer so as to define a dimension of said floating gate member;

subjecting said substrate to an elevated temperature so as to grow an oxide region at edges of said floating gate member such that a thicker oxide develops at said edges of said floating gate member when compared to said oxide layer at the central portion of said floating gate member;

whereby said edges of said floating gate are protected by a thicker oxide region thereby reducing undesirable loss of charge from said floating gate member to overlying structures.

2. The process defined by claim 1 wherein said first oxide layer is grown to a thickness of approximately 400-500 Å

thick.

3. The process defined by claim 2 wherein said oxide at said edges of said floating gate member is grown to a thickness of approximately 700 Å

.